regarding the Stratix IV GX FPGA development kit, see:
http://media.digikey.com/pdf/data%20sheets/altera%20pdfs/dk-dev-4sgx230n-c2.pdf specifically, regarding pages 40-49 in the Stratix IV E FPGA Development Board Reference Manual, see:
http://www.altera.com/literature/manual/rm_sive_fpga_dev_board.pdf more specifically, regarding a statement on page 41 in the above reference manual doc says, "The HSMC interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels."
question: Can I configure the LVDS channels to transfer data all in one direction or the other; so for example, instead of having 17 full duplex LVDS transmit/receive channels, I can have 34 LVDS transmit channels per HSMC I/O port?
context of this question: I have a 4 GS/s DAC (digital to analog converter) with 12 bit resolution in mind that I want to attached as a daughter card to the HSMC I/O port of the Stratix IV GX board. There are a total of 48 input channels into the DAC (each of 4 samples is 12 bit wide). To reduce DAC resolution, I can use 8 instead of 12 bits; therefore requiring 32 LVDS inputs.
Given this context, please address the above question. Thanks.
Eric
