Question about PLL reconfig

[Altera_Forum]

Hi, 

I have been trying to reconfigure for couple of days now and i failed horribly. I am hoping you will shed some light to my doubts;  I have been following documentation for trying to reconfigure my PLL; 1. http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf 2. http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf 3. http://www.altera.com/literature/an/an507.pdf ( I understand that this is a tutorial for cyclone III device, but i figured the procedure will be the same because this is the only procedure i found that shows how to configure the PLL. All the other documents just gives reference info but no instructions.)  currently my PLL is configured as following;  inclock - 50 MHz C0 - 7.5 MHz C1 - 0.004 MHz  I created a ill reconfiguration module and connected the ports as shown in either of document 1(page 13 figure 9) and document 3(page 3 figure 2)  The All the inputs for the reconfiguration module is coming from my NIOS processor(write_param, read_param etc etc..) Inclock for PLL reconfiguration module is 50 MHz and reset comes from a push button KEY[0]   *********************************************************************************************** This is how the program flows *********************************************************************************************** When the program starts, i generate two clock cycles C0 and C1 operating at 7.5 MHz and 0.004 MHz respectively after about 10 sec, i want the clock frequency of C0 to change to 7.0 MHz and after another 10 second, i want my C1 clock frequency to change to 0.005 MHz.  Following is a snippet from my NIOS II code;  #include "includeme.h" # include "piodriver.h" int main() { printf("Hello from Nios II!\n"); // This is the first 10 sec delay usleep(10000000); // Set counter type to C0 output_data(COUNTER_TYPE_BASE, 0x4); // Set counter_param to bypass(4'b0100) output_data(COUNTER_PARAM_BASE, 0x4); // Set data_in to 1 output_data(DATA_IN_BASE, 0x1); // Assert high for 10usec output_low(WRITE_PARAM_BASE); usleep(100); output_high(WRITE_PARAM_BASE); usleep(100); output_low(WRITE_PARAM_BASE); // Assuming busy is high at this point for 100ms // Busy will be alot less then this, but i used 100 just to be sure usleep(100000); //output_high(RECONFIG_BASE); //usleep(10); //output_low(RECONFIG_BASE); // Set counter type to N output_data(COUNTER_TYPE_BASE, 0); // Set counter_param to bypass(4'b0100) output_data(COUNTER_PARAM_BASE, 4); // Set data_in to 1 output_data(DATA_IN_BASE, 50); // Assert high for 10usec output_low(WRITE_PARAM_BASE); usleep(100); output_high(WRITE_PARAM_BASE); usleep(100); output_low(WRITE_PARAM_BASE); usleep(100000); //output_high(RECONFIG_BASE); //usleep(10); //output_low(RECONFIG_BASE); output_high(RECONFIG_BASE); usleep(100); output_low(RECONFIG_BASE); // SET COUNTER_TYPE TO M output_data(COUNTER_TYPE_BASE, 1); // Set counter_param to bypass(4'b0100) output_data(COUNTER_PARAM_BASE, 4); // Set data_in to 1 output_data(DATA_IN_BASE, 7); // Assert high for 10usec output_high(WRITE_PARAM_BASE); usleep(100); output_low(WRITE_PARAM_BASE); usleep(100000); // Finally reconfigure the PLL output_low(RECONFIG_BASE); usleep(100); output_high(RECONFIG_BASE); printf("RECONFIG COMPLETE"); return 0; }  After doing this, my PLL doesn't get reconfigured. And after studying all three documents, i think i need help to solve this problem. PLEASE any help would be greatly appreciated.   Best Regards, Pratish Karmacharya

[Altera_Forum]

Anyone? Any help?