Question on DDR2 DRAM of CycloneIII board

[Altera_Forum]

Hi all, 

 Currently I have a Cyclone III board featuring Cyclone III EP3C120. The board has 256 MB of dual-channel DDR2 SDRAM memory with a 72-bit data width. According to the reference manual: "The data bus can be configured as two separate buses of 32 bits each, or a single 32-bit and a single 40-bit bus."  My question is: can I configure the data bus simply as 64bit instead of two separate buses of 32bits each?  Thanks!

[Altera_Forum]

Hi guys, 

 Another question. In cycloneIII board, the DRAM is divided into top bank and bottom bank. The top bank has two clock pairs (one pair drives 32bit DQ, the other pair drives 8bit DQ), and the bottom bank has one clock pair (this pair drives 32bit DQ).  if I am using 64bit DQ(32bit from top bank, 32bit from bottom bank), should I generate two pairs of clocks to drive 32bit each or just use one pair of clock to drive both top and bottom bank? I am asking this question because in Quartus II "DDR2 DRAM high performance controller", there's one parameter "output clock pairs from FPGA" where I can choose 1 ~ 6 for this parameter.  Thanks a lot!

[Altera_Forum]

Did you get a single controller working on Cyclone 3C120 board with two clock pairs - one for top and one for bottom?

[Altera_Forum]

I don't have an answer to your question but I'm curious what board you're using. I looked and looked for a board with a 36 or 72-bit memory path and didn't find anything. Now I've settled for something 32-bits wide and I'll just read 18-bits at a time and assemble what I need but I'm curious for the future.

[Altera_Forum]

Altera cyclone III FPGA Dev board has 32 bits on bottom and 40 bits on top side interface

[Altera_Forum]

How on earth did I miss that one? Oh well, the DE2-115 I got instead has enough memory and more interesting IO ports. Thanks.