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Altera_Forum
Honored Contributor I
710 Views

Questions about SDRAM memory test on CyIII DK

I am using the Cyclone III Development Kit with the Triple Speed Ethernet Reference Design that has 128MB SDRAM configured. I am running the Memory Test program built from the Nios project template. 

 

The system.h file gives me a starting address of 0x10000000 for the SDRAM. When I run the memory test starting at the base address and on up through the first 96K of address space the program will hang as if something important was overwritten and is no longer running. If I start the memory test after the first 96K above the base address it has no problem. 

 

My questions are: 

 

Am I using the right address for the SDRAM in this design? 

 

If so, is there anything in the lower part of the memory space that is being used elsewhere that I should know about? If not, should I assume that the memory is bad in that address range?
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2 Replies
Altera_Forum
Honored Contributor I
29 Views

The memory that is being tested cannot be used for Reset or Exception Addresses or (to be safe) any linker sections. 

 

To me, it sounds like the Exception Address is pointed to this memory. You'd have to open the Nios II in SOPC Builder, point the exception address elsewhere, re-generate in SOPC Builder, re-compile in QII...and then re-run the memory test. 

 

Or, you could just live with where it does work.
Altera_Forum
Honored Contributor I
29 Views

Thanks for the tip. Yes, that is exactly what the problem is. The exception address is assigned to SDRAM at offset 0x120 (absolute address 0x10000120).