We have a VHDL MAC core (supporting RGMII and GMII) and we are trying to port a RGMII design to a Cyclone 10.
We found out ALTDDIO (both IN and OUT) are no more supported adn that we should use an GPIO IP core.
First question, we dont want to use IP cores, we would like to instantiate it, we found a cyclone10gx_ddio_in component in package cyclone10gx_components, but we cant find a way to instantiate it.
Second: we found this one (https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...) which sounds not promising to me...
Is there any way to use simple double data rate IO in a cyclone 10?
Thanks in advance for any help
Pls see my comment below.
- Is there any way to use simple double data rate IO in a cyclone 10 ?
- I presume you are Altera veteran user that's familiar with WYSIWYG or megawizard usage model.
- Yet, the design practice has changed. Right now we only recommend customer to use IP core and not some low level design instance anymore to avoid breaking Quartus design compilation flow.
- The replacement IP for DDIO in Cyclone 10 GX device is indeed GPIO IP.
- Regarding RGMII support on Cyclone 10 FPGA
- Unfortunately as explained in the KDB link that you found out as well, RGMII can't be supported anymore on Cyclone 10 GX due to FPGA GPIO circuit architecture changes
- We can only advise customer to switch to GMII or SGMII
I apologize for the inconvenience and appreciate your understanding at the same time.
I have not hear back from you for close to 1 month.
Hopefully my earlier explanation is clear to you.
For now, I am setting this case to closure.