I want to use Cyclone V - 5CGTFD9E5F35I7 in one of my projects. I've got to route the following interfaces:
FibreChannel - 5 lines [ 2112 Mbit/s ]
FibreChannel - 1 line [ 250 Mbit/s ]
Serial RapidIO - 2 lines [ 5 Gbit/s ]
LVDS - 19 lines rx/tx [ 800 Mbit/s ]
And DDR3 (x32 data) memory (1066).
The memory is placed in 3B and 4A FPGA banks. 8A bank is completely used by LVDS. The 1st SRIO in B3L bank, second use the B0L bank with clocking from corresponding pins.
When I try to place FibreChannel's i see error that clock dividers or pll are not enouth.
* Is there any possibility to place all necessary interfaces in the amount needed on the present FPGA?
* Or, I've got to refuse any interfaces?
* What about clocking? How can I feed all the interfaces?