Can any one you tell me does the RapidIO from Altera is supported by the Cyclone III FPGA Development Kit containing Cyclone III EP3C120F780 FPGAThis question arise because in the RapidIO MegaCore Function user guide it is there in the Table 1–2. Device Family Support that Cyclone III Final (4th row in table) Cyclone III LS Preliminary (5th row in the table ) but it also tells the FPGA Cyclone III (EP3C55F780C6) is supporting the RapidIO. OBSERVE THE DIFFERENCE IN NUMBERING OF THE TWO FPGA'S HERE We have the Board Cyclone III FPGA Development Kit containing Cyclone III EP3C120F780 FPGA can we use this for the incorporating the RapidIO IP RapidIO is having Baud rate of 3.125Gbaud with external SERDES in cyclone III . Also tell me what is actually meant by the external SERDES????
IIRC you can use the RapidIO on the EP3C120F780, but you will need an external PHY chip for the actual link. The FPGA will use a parallel bus to talk to the PHY chip, that will do the serial conversion (hence the "external serdes').
--- Quote Start --- IIRC you can use the RapidIO on the EP3C120F780, but you will need an external PHY chip for the actual link. The FPGA will use a parallel bus to talk to the PHY chip, that will do the serial conversion (hence the "external serdes'). --- Quote End --- Hi, Thank you for your valuable reply Daixiwen, I have an another question regarding the external serdes. I am working on the very high speed serial communication, for this I am using the rapidIO IP from altera, we have the cyclone III EP3C120F780 FPGA Devlopment Kit. Is it possible to write a code or get as an IP from altera (functional equivalent of serdes) and put it together with RapidIO IP into the FPGA and check the functionality of serial communication or it is complusary to use external phy chip for the actual link. Please do guide me regarding this as soon as possible....
If you need to communicate with another SRIO compliant component, you will need a board with a serdes. If you just want to have a communication between two FPGAs, it may be possible to connect the two rapidIO IPs through a custom logic that would act like two serdes. I haven't looked at the interface with the serdes so I don't know how this should be done though.
Hi,If we want to check just the serial communication within the Single RapidIO using only one FPGA ..... Like connecting the TXP,TXN lines with the RXP,RXN lines can we use the cyclone iii ep3c120f780 fpga Board....for this...
I think that you could connect the external PHY interfaces between two RapidIO IPs inside one FPGA, and it should work... But I never tried it.What do you want to test exactly? Using such a setup it won't be a serial interface anyway, but an 8-bit parallel. You won't test the interface with an external serdes either.
Hi,Actually we don't have any other altera kit having embedded transceivers in them. So thought of doing the serial communication using cyclone III EP3C120F780 FPGA. But now it's not serial communication means it's not worth doing it right??? We need to establish serial communication that works at very high speed.. for that we are using the IP's from the Altera. Can you suggest the Cyclone IV GX DK-DEV-4CGX150N board for this purpose..because we need to purchase this Board now so asking to make sure we can achieve high speed serial communication using cyclone IV GX Is that alright with this new board???
It seems that this kit only uses the GX transceivers for the PCI express interface and maybe the gigabit Ethernet. There doesn't seem to be any other plug on the board directly connected to a transceiver.You'll either need an HSMC board with a serdes, another development kit, or do your tests on the PCI express link with the PC instead of RapidIO.
The cyclone iv gx transceiver starter kit (http://www.altera.com/products/devkits/altera/kit-cyclone-iv-starter.html) can be modified to connect the transceivers to SMA connectors, but unfortunately the FPGA package doesn't support RapidIO.The transceiver signal integrity development kit, stratix iv gx edition (http://www.altera.com/products/devkits/altera/kit-signal_integrity_sivgx.html) has everything you seed to test RapidIO but it probably overkill (and expensive).
Thank you Sir for your valuable replyThe cost of the transceiver signal integrity development kit, stratix iv gx edition (http://www.altera.com/products/devkits/altera/kit-signal_integrity_sivgx.html) is more for us...... If we goes for the tests on the PCI express link.....will the cyclone IV GX suits this application.....
Hi,Finally We have the stratix II GX EP2SGX90F1508C3 FPGA Board and now want to develop a system that works as very high speed serial Interface using the transceivers present in the FPGA. For this purpose which is the IP from the Altera that suits better for this application so that we can achieve the target at earliest since we have less time with us.