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Hello,
I am trying the re-compile the bts_hsmc example (high speed transceivers) UNDER altera\10.1\kits\cycloneIVGX_4cgx150_fpga\examples\board_test_system\bts_hsmc I get a bunch of errors about wrong voltage levels and PMA default values. Has anyone managed to re-compile this example ? I am using version 10.1 Build 197 Web edition Service pack 1. Many thanks folks. RGLink Copied
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Just to clarify: Other examples from this same kit compile without any error.
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update:
I installed the full version of Quartus : 10.1 Build 197 01/19/2011 Srp1 The problem remains the same – errors during compilation. Below is a printout of the erros: error: rx pma element 'nios_bts:nios_bts_inst|hsmc_xcvrs_0:the_hsmc_xcvrs_0|hsmc_xcvrs:hsmc_xcvrs_0|hsmc_xcvrs_top:hsmc_xcvrs_top_i|nios_bts_port_core:nios_bts_port_core_i|c4gx_basic_x4_3g:c4gx_basic_x4_3g_inst|c4gx_basic_x4_3g_alt_c3gxb:c4gx_basic_x4_3g_alt_c3gxb_component|receive_pma0' has an illegal signal_detect_hysteresis_valid_threshold parameter setting of 1 info: "14" is a legal value error: rx pma element 'nios_bts:nios_bts_inst|hsmc_xcvrs_0:the_hsmc_xcvrs_0|hsmc_xcvrs:hsmc_xcvrs_0|hsmc_xcvrs_top:hsmc_xcvrs_top_i|nios_bts_port_core:nios_bts_port_core_i|c4gx_basic_x4_3g:c4gx_basic_x4_3g_inst|c4gx_basic_x4_3g_alt_c3gxb:c4gx_basic_x4_3g_alt_c3gxb_component|receive_pma0' has an illegal signal_detect_hysteresis parameter setting of 2 info: "4" is a legal value info: "8" is a legal value [i get these two errors 8 times – for each channel] I fixed these errors manually and got a new error: Error: One or more transceiver channels are configured at a data rate that is higher or equals to 2.97 Gbps which requires that you follow updated pin connection guidelines. For technical details on the updated pin connection guidelines and to download a patch to continue compilation, refer to Altera Knowledge Database solution number rd10182010_86. Does anybody have an idea what else I can try ? :mad: :mad: does somebody from altera care to comment ? :mad: :mad: Many thanks,
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