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Altera_Forum
Honored Contributor I
1,602 Views

Read then Write data on SRAM DE2 board

I am doing my final year project related to image processing. i write the image HEX file into DE2 SRAM board using DE2 control panel and trying to load the image data from each location of SRAM then process it. But i face the problem which read a data from location A then write the data into location B (copy the data from location A then overwrite the data on location B within 2 clock cycles of 50Mhz. But i get the result with all HIGH (0xFFFF) (which are not desired data i set for location A and B by using control panel before run my code) . But i get the undesired result by my vhdl code. Hope anyone help me fix this and would appreciate your help. :) Here is my code: 

 

----------------------------------------------------------------------- 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_arith.all; 

 

entity test1 is 

port(clock : in std_logic; 

LEDR: out std_logic_vector(15 downto 0); 

SRAM_ADDR: out std_logic_vector(17 downto 0); 

SRAM_DQ: inout std_logic_vector(15 downto 0); 

SRAM_CE_N: out std_logic; 

SRAM_OE_N: out std_logic; 

SRAM_WE_N: out std_logic; 

SRAM_UB_N: out std_logic; 

SRAM_LB_N: out std_logic 

) ; 

end test1; 

 

architecture inside_top_level_entity of test1 is 

 

signal address: std_logic_vector(17 downto 0); 

signal data: std_logic_vector(15 downto 0); 

signal count:integer:=0; 

signal count_1Hz : integer:=0; 

shared variable twosam_add : integer:=1;  

type state_type is (s0, s1); 

signal state : state_type; 

 

begin 

 

SRAM_CE_N <= '0'; 

SRAM_UB_N <= '0'; 

SRAM_LB_N <= '0'; 

SRAM_OE_N <= '0'; 

 

process (clock)  

begin 

 

if clock'event and clock='1' then 

 

case state is 

 

-----read data from address 1 of SRAM 

 

when s0=> 

SRAM_DQ <= (others=>'Z'); 

SRAM_WE_N <= '0'; 

address <= conv_std_logic_vector(twosam_add,18); 

SRAM_ADDR <= address; 

data <= SRAM_DQ; 

state<=s1; 

 

-----write data to address 0 of SRAM 

 

when s1=> 

twosam_add:=0; 

address <= conv_std_logic_vector(twosam_add,18); 

SRAM_ADDR <= address; 

SRAM_WE_N <= '1'; 

SRAM_DQ <= data; 

 

end case; 

end if; 

end process; 

 

LEDR<=SRAM_DQ; 

 

end inside_top_level_entity;
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4 Replies
Altera_Forum
Honored Contributor I
173 Views

This code is not how you would write and read an SRAM device. 

 

Interfacing to SRAM requires adhering to the data sheet timing waveforms for read and write. For example, there is a PDF in this thread that shows the waveforms: 

 

http://www.alteraforum.com/forum/showthread.php?t=31457 

 

There is also some code in a zip file. Its not exactly the code that you need (since that would be too easy), but its enough to get you started. 

 

If given the task to read/write an SRAM location, I would recommend implementing an Avalon-MM slave SRAM interface (or using Altera's existing IP), and then perform Avalon-MM master read/write accesses. The Avalon-MM master access logic is trivial to write, and the timing complexity of the SRAM is hidden from your master logic. The master could also perform read/write access to on-chip FPGA RAM, and the logic does not need to change. 

 

You should also learn how to use Modelsim. Cypress and other SRAM manufacturers have SRAM models written in VHDL that you can use to test your controller logic. It does not matter whether or not the model matches the exact part number on your board, as you controller should be written such that the timing can be configured, eg., via generics. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
173 Views

Thanks dwh. 

 

But how to implementing the Avalon-MM slave and master ? Can you please post any link for guide me to do this? And i did read some post on this forum it is using NIOS II. is it have to control it by using C code? My supervisor was request me to implement this project using vhdl... My project is about image processing that load data from SRAM, process it and then write it onto SRAM, then use control panel to display the image vector on VGA monitor. I am using quartus 2 version 9.0 and DE2 board with cyclone 2 device. And sorry that i ask so many because i am just a beginner of vhdl and quartus 2...
Altera_Forum
Honored Contributor I
173 Views

 

--- Quote Start ---  

 

But how to implementing the Avalon-MM slave and master? 

 

--- Quote End ---  

 

 

Read the Avalon Specification, and start by using Altera's existing IP.  

 

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 

 

--- Quote Start ---  

 

Can you please post any link for guide me to do this? 

 

--- Quote End ---  

 

There should be an example with the DE2 installation. 

 

Browse through the examples on the University Program web site: 

 

http://www.altera.com/education/univ/unv-index.html 

 

Click on the links below "Educational Materials". 

 

Altera also has some design examples: 

 

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html 

http://www.altera.com/support/examples/nios2/exm-avalon-memory-slave.html 

 

Use Modelsim to simulate these examples. 

 

 

--- Quote Start ---  

 

And i did read some post on this forum it is using NIOS II. is it have to control it by using C code? My supervisor was request me to implement this project using vhdl... My project is about image processing that load data from SRAM, process it and then write it onto SRAM, then use control panel to display the image vector on VGA monitor. I am using quartus 2 version 9.0 and DE2 board with cyclone 2 device. And sorry that i ask so many because i am just a beginner of vhdl and quartus 2... 

--- Quote End ---  

 

 

Its ok that you ask questions, and thank-you for telling us that you are a student.  

 

Members of this forum are more than happy to help students, but in general we prefer to see that the student has attempted to figure out the problem themselves. You've started out the right way by indicating what you have been asked to do. 

 

The first thing you need to do is to get each component working. For example, how do you display an image on VGA? The DE2 board comes with an example that outputs an image on VGA. Look at that code, understand how they did it. Was it with software alone? Was it with hardware alone? Was it a combination of the two? Is the VGA interface they created for that design appropriate for your design. 

 

You need to systematically create each component and test it. You can use VHDL only, or NIOS II + VHDL. That aspect does not really matter. What your supervisor will want to see is that you had a specification to meet, and you met it. While designing your system, you should discuss what you are doing with your supervisor to confirm that your solution meets with his/her approval. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
173 Views

 

--- Quote Start ---  

Read the Avalon Specification, and start by using Altera's existing IP.  

 

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

 

 

There should be an example with the DE2 installation. 

 

Browse through the examples on the University Program web site: 

 

http://www.altera.com/education/univ/unv-index.html 

 

Click on the links below "Educational Materials". 

 

Altera also has some design examples: 

 

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html 

http://www.altera.com/support/examples/nios2/exm-avalon-memory-slave.html 

 

Use Modelsim to simulate these examples. 

 

 

 

Its ok that you ask questions, and thank-you for telling us that you are a student.  

 

Members of this forum are more than happy to help students, but in general we prefer to see that the student has attempted to figure out the problem themselves. You've started out the right way by indicating what you have been asked to do. 

 

The first thing you need to do is to get each component working. For example, how do you display an image on VGA? The DE2 board comes with an example that outputs an image on VGA. Look at that code, understand how they did it. Was it with software alone? Was it with hardware alone? Was it a combination of the two? Is the VGA interface they created for that design appropriate for your design. 

 

You need to systematically create each component and test it. You can use VHDL only, or NIOS II + VHDL. That aspect does not really matter. What your supervisor will want to see is that you had a specification to meet, and you met it. While designing your system, you should discuss what you are doing with your supervisor to confirm that your solution meets with his/her approval. 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Hi Dave,  

Thank you for your replies and guide me patiently. I really appreciate your help and i would take note what you had said. =) And sorry that i late reply because i am busy to program my image processing simulation part. I will read the materials you suggested after i done my image processing part.  

 

But i am stuck now in my image processing part. I am using FFT megafunction in my image processing but can't get the desired output. The problem that i had face is i cannot get the output of last FFT block only since it's size(eg 7 points) is not same with the previous FFT blocks size (eg 8 points),i can get the previous FFT blocks and result are correct. I had follow the instruction Dynamically changing the FFT Size in the manual,mentioned that the sink_ready will be deassert when FFT block size changed, is it FFT will block the incoming data input or temporary save it in the FFT until the sink_ready is asserted? But i try to follow the manual instruction still can't get the output of the last FFT block. Anyone face this problem before or any idea to solve it?  

 

My FFT parameters setting: 

cyclone 2 device 

256 points 

32 bit data width 

variable streaming with single precision floating point. 

 

Here my waveform attached with 8 and 7 points FFT for testing. I had refer to the Figure 3-8 (Dynamically Changing the FFT Size) of FFT megafunction. Thanks for your help.
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