Reference clock for PLL

[Fresh_Leon]

Dear, 

In Arria 10 Datasheet, the max frequency of three PLL (CMU, ATX, fPLL) is 800MHz (Page 28).

However, in a10gx_si_e4 schematic, I found that Y6 oscillator (Si570) was programed to 875MHz.

Is this OK?

[EngWei_O_Intel]

Hi Yang Ni

Thanks for your inquiry. Can you share the link of a10gx_si_e4 schematic?

Thanks.

Eng Wei

[Fresh_Leon]

Dear, Wei

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/signal-integrity-dev-kit/arria10GX_10ax115sf45_si_v15.1.zip

Schematic are in zip file. After you un-zip it, the schematic should be in following path.

 "arria10GX_10ax115sf45_si_v15.1\board_design_files\arria10_10ax115s2f45i2sg\schematic"

Brs,

Leon

[EngWei_O_Intel]

Hi Yang Ni

I still need some time to check with the board team before getting back to you. 

Thanks.

Eng Wei

[Fresh_Leon]

It's OK.

Take your time.

Brs,

Leon

[EngWei_O_Intel · Accepted solution]

Hi Yang Ni

The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.

For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.

Thanks. 

Eng Wei

[Fresh_Leon]

Hi, Wei

Understood.

Thanks.

Brs,

Leon

[EngWei_O_Intel]

Cool Leon. I will transition this case to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you for contacting us.

Eng Wei

[EngWei_O_Intel]

Hi Leon

You can set this case to closure too if there is no further request needed on this case.

Thanks.

Eng Wei