FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5892 Discussions

Regarding maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board

SnehaRao
Novice
902 Views

This question is regarding the maximum achievable bandwidth via the PCIe (v3, x16) interface for the Intel d5005 board.

We did the following tests:

A) Using the streaming_dma_afu example for bandwidth. - 6.7 GBps read, 7.6 GBps write
B) Using the nlb_mode_0 example in LPBK1 mode. - 9 to 9.5 GBps
C) Using OpenCL based 'aoc diagnose all'. - 8.4 GBps

Could someone please let us know why the achievable bandwidth in these tests is almost half of the official specification?

0 Kudos
6 Replies
EngWei_O_Intel
Employee
884 Views

Hi SNEHA

May you guide us on which part of the official specification doc you are referring to? Thanks.

Eng Wei

0 Kudos
SnehaRao
Novice
875 Views

Hi !

The datasheet of D5005 card (link here, go to pg 3 of 29)  specifies it is a PCI Express Gen 3 x16 compliant card. According to the specification of PCI Express, Gen 3 x16 should give bandwidth of 15.75 GB/s (source here). However we are unable to achieve it.

Regards

Sneha

 

0 Kudos
EngWei_O_Intel
Employee
868 Views

Hi SNEHA 

The spec you are mentioning here is the ideal case for a PCIE transfer rate. The testing you are doing involve the overhead of data transfer from host to FPGA and back to host. We can't compare both the numbers.

Thanks.

Eng Wei

 

 

0 Kudos
SnehaRao
Novice
861 Views

Hi!

Thank you for your response. I agree that data transfer from host to FPGA and then back to host involves some overhead and thus the specified bandwidth cannot be reached. However, could you kindly let us know what is the practically achievable maximum bandwidth via PCIe (v3, x16) for d5005 board (considering the overhead)? And, how to achieve it? It would be of great help to us.

Thank you

Regards

Sneha

0 Kudos
EngWei_O_Intel
Employee
854 Views

Hi Sneha

You can refer to section 5. Running FPGA Diagnostics of https://www.intel.com/content/www/us/en/programmable/documentation/edj1542148561811.html#iyl1548632576241

for FPGA diagnostic sample test. The sample results might be different involving various factors of the testing environment.

 

Thanks.

Eng Wei

0 Kudos
EngWei_O_Intel
Employee
792 Views

Hi Sneha

We do not receive any response from you to the previous answer that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Thanks.

0 Kudos
Reply