Aloha is a predecessor of Ethernet which has a maximum theoretical efficiency near 50%. Distributed Queuing Switch Architecture was invented for cable TV as a ~100% universal MAC for simultaneous synchronous and asynchronous flows on a single channel, however, the first demonstrations have occurred on Internet of Things radio networks Zigbee and LoRa, winning an IEEE and Google Research Award.
The CTTC network: http://technologies.cttc.es/iotworld-experimental-platform/iotworld-dq/
The link to the LoRa work from Bucknell http://github.com/Kuree/DQN
Attached, please find the first fully drawn protocol specification to be used as a starting point for interoperable DQ networks which can coexist with any IEEE 802.x.x. Please also review a more recent 5G simulation where DQ replaced Aloha in the 5G Random Access Channel. https://ieeexplore.ieee.org/document/8880524
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Hi Michael and thank you for asking for clarification. When I say "replacing Aloha", we're talking about substituting a transmission scheme which operates as any other random access protocol and can dynamically shift to a reservation protocol at higher loads. It will still be a contentious network, however, collisions can only occur in the control minislots which are then resolved in a secondary queue, as opposed to the primary global transmission queue. The result is an actual performance curve that closely follows theoretical perfection, without the typical degradation that comes with more nodes and more traffic.
A network interface card could be an exemplary implementation. However, in addition to running Ethernet, the FPGA needs to be designed with a "dual MAC" for interleaving legacy and novel flows. This coexistence scheme then presents the ability to have a migration path to high performance networks which do not have Ethernet's fundamental flaw (that it does not work well without middle hardware). Perhaps we should call it "Elegant Ethernet", but the engineers who invented it at Illinois Institute of Technology for cable TV video networks named it Distributed Queuing.
As you can see from the links I've posted, all of the more recent work has been in wireless. However, the lower layer 2 MAC specification that we are proposing should also be considered for terrestrial applications served by new type of NIC. If a pure DQ switch, we would expect packet efficiency to get the same type of improvement realized in the Zigbee and LoRa radio demos -- packet efficiency went from 50% to 98%.
In the CSMA/DQ coexistence model, efficiency would be slightly lower since time would need to be devoted to legacy devices that have no knowledge of DQ switching. However, this is a small price to pay for a migration path to future networks which do not have in Ethernet's well known performance and security constraints.
Thanks very much,
Base on your inquiry, we have specific forum for these issues and I will be transferring this thread for faster response.
Intel® Customer Support
Thanks for using Intel forum community and provide detail explanation but sorry, I still don't quite get your ASK here on exactly what kind of support that you need from Intel FPGA
Are you looking for Intel FPGA to provide some custom protocol IP solution ?
Just FYI... This FPGA forum community is meant to help out if customer encounter issue in using FPGA or you need help in using certain FPGA IP solution
but now you gives me a feeling like you are asking for design service to provide "custom protocol IP solution"
I found extra hidden note in system that may reflect your question asked here
I presume you are developing this "dual MAC" IP yourself and is looking for existing Intel FPGA dev kit that's able to support it ? Correct me if my understanding is wrong.
However, we do have website link that showcase all available dev kit board with detail user guide doc that explained on the capability of the dev kit board.
DQ is a novel solution but it is not a custom solution since it would become a defacto standard that Intel would include in its products without needing to collaborate with standards bodies.
There has never been a near-perfect universal MAC, so if someone came to Intel with a big idea and needed help, it is hoped that Intel would understand the "brighter light bulb" that would be an effective doubling in throughput, as well as the resulting societal impact. Again, we are talking about gaining back the best features of circuit switching in a packet switched framework.
Perhaps we can kick this up to a product manager since the support I need is for Intel products to support a novel MAC with a proven migration path for any IEEE 802.x.x. The Cyclone V would probably be a good fit per the Mathworks site, so then the only thing you'd need from me is the intellectual property I'm attempting to contribute.
A Google Research Award from Vint Cerf, an IoT World Cup for security, and an IEEE Award for the first demonstration should count for something? If not, then I give up and DQ will just continue to sit on the shelf. Conversely, I'd prefer DQ become a global IoT standard without winners and losers in the chip space.
I appreciate you bring brilliant idea to Intel but unfortunately this Intel FPGA forum community is not the right place to discuss about your idea support.
Perhaps we can kick this up to a product manager since the support I need is for Intel products to support a novel MAC with a proven migration path for any IEEE 802.x.x.
The official channel will be for you to contact your local Intel distributor or Sales team then they should be able to hook you up with appropriate Intel Marketing/Product Manager/Business Unit Sponsor to evaluate your idea further.