Routing rule of LVDS - Intel Community

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

Routing rule of LVDS

528 Views

Hi experts

What's the routing rule of LVDS? For example, differential pair’s intra length matching, Clock-to-Data length matching, maximum trace length, etc.

Or any guide for reference?

Link Copied

2 Replies

439 Views

Hi ,

I am kindly requesting to follow the guidelines provided by altera

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html

Copy link

439 Views

Hi ,

Kindly let me know if you need further assistance

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.