i have s10-DX kit which I am planning on using for developing a design. for this design i intend to get DMA over PCIe as basic functionality; and i will develop my user logic on top of it.
the SW package link i got (from kit homepage) has a sample PCIe design with associated SW. however there is no document which can help in understanding RAW lines of code. I will need details about the design to understand how can i use and enhance it for my usage.
You may generate the design directly from quartus. Then follow the steps using this document.
This document complete describe the step to generate the design. Also the step to run it on the s10 dx dev kit.
I am able to follow the guide, able to generate example design and generate SOF file.
next task - I want to extended the config address space mapping for PCIe IP above 0xFFh (to use and define PCIe DVSEC capability registers), and assign some predefined values to certain addresses in “Read Only” mode.
While generating PCIe IP through IP catalog , there was no option to define extended config space or DVSEC registers. so in order to do what i want, I started reviewing RTL files; generated by PCIe IP compilation in Quartus. Many of the files appears to be encrypted (see the screenshot); and I can not read the RTL code associated with these modules. Do you know how to decrypt these RTL files? So I can read them and identify lines of code, which needs to be modified.