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AleCampla
Novice
161 Views

S10 MX PHY: signal rx_is_lockedtodata unstable during hardware test

Hi,

I am trying to establish 1G communication between my laptop and a dev kit with s10 MX.

My designed is based on the 1G/2.5G linked here.

As the devkit does not have an RJ45 connector (and as i need only one transceiver line) I am using : 

1) https://www.fs.com/de-en/products/72588.html

2) https://www.fs.com/de-en/es/products/66616.html?currency=EUR&paid=google_shopping&gclid=CjwKCAiAp5ny...

But rx_is_lockedtodata signal is not stable, it continuously flickers, causing the rx_digitalreset from the reset controller to flicker as well (picture from signaltap attached).

I thought it might be due to a failure in the auto-negotiation. I checked the PHY registers with the system console, and that's what I get:

% CHKPHY_STATUS
PHY Control = 0x140
PHY Status = 0x9
PHY ID 0 = 0xC01A
PHY ID 1 = 0xC0CA
Dev Ability = 0x1A0
Partner Ability = 0x0
AN Expansion = 0x0
IF mode = 0x0

According to the PHY documentation (Table 15) the Bit[3] of the status register set to 1 means that there is auto-negotiation capability.

Bit [12] of the control register corresponds to AUTO_NEGOTIATION_ENABLE and for me it is currently at 0, but I imagine I need to switch to 1.

But when I try to use the command "SETPHY_CL_37_AN" that would send "reg_write 0x00018000 0x00 0x1140" (commands taken again from the example designs here), the PHY control register remains at 0x140.

I checked addresses and bits. And their are actually correct.

 

Question one: is actually auto-negotiation the problem?

Question two: why I am not capable of writing that specific register? (I can switch between 1G/2.5G config without problems).

 

It's worth to mention that in simulation the rx_is_lockedtodata gets locked.

In that case I inject (random) data into the gmii side of the PHY and loopback tx and rx.

 

Thanks in advance for the help.

Alessandra

 

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2 Replies
SengKok_L_Intel
Moderator
154 Views

Hi,


This does not look like the AN issue, and this is uncertain if the 40G module can run at lower data rate.


Question:


a) Does the Laptop support AN and is this enabled? If this is enabled, you may try to disable it.

b) Did you first set the channel base address correctly below running other tests?

e.g. SET_CHANNEL_BASE_ADDR $channel

c) Could you please try to set the serial loopback and see if the locktodata is asserted?

e.g. SETPHY_SERIAL_LLPBK

d) Could you please connect it to an external loopback module (TX to RX) and run the following test?

e.g. TEST_EXT_LB {channel speed burst_size}


Regards -SK


SengKok_L_Intel
Moderator
119 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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