Hello,
I am writing a code to access SD card on DE2 board. i have started with it and facing few problems with unexpected latch(es).
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always @(state)
begin
case (state)
st_idle: -----
st_CMD0: begin
if (i == 8'd40)
begin
i = 8'd0;
cmd_0 = 0;
SD_CMD = crc7[6]; // send MSB of crc7
nx_state = st_crc7;
end
else
begin
cmd_0 = 1;
SD_CMD = CMD0[39-i]; // make sure MSB is sent first
crc7 = crc7 << 1; //crc = crc << 1
if (crc7[7] ^ CMD0[39-i]) // moved to crc output logic
crc7 = crc7 ^ 8'h09;
i = i + 8'd1;
nx_state = st_CMD0;
if (i%8 == 0) // moved to crc output logic
crc7 = crc7 & 8'h7F;
end
end
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This is the part of my code where the following warnings appear;
Warning (10240): Verilog HDL Always Construct warning at sdcard.v(91): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at sdcard.v(91): inferring latch(es) for variable "SD_CMD", which holds its previous value in one or more paths through the always construct
I do understand here that 'i' has its old and current value in the same clock, but how to avoid it? And have no clue about variable 'SD-CMD'. I expect you might have come across such warnings & solved it. If so then plz help me.
Thanks in advance.
Vivek.
