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SDC timing constraint cannot be applied during compilation

Winston_Sun
Beginner
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Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not match with a clock") (fig 2) thereby some script in the top level qsys sdc file (from intel JESD204C example design) is not applied to the design compilation. I try to copy the ignored script (fig 3) into the timing analyzer GUI console and it solved the timing violations.

Script as below:

set_clock_groups -asynchronous -group [get_clocks {mgmt_clk}] -group [get_clocks {ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk}] -group [get_clocks {u_j204c_rx_tx_ss|core_pll|core_pll_clk_1x u_j204c_rx_tx_ss|core_pll|core_pll_clk_2x u_j204c_rx_tx_ss|core_pll|core_pll_refclk }] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|tx_clkout|ch0}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch0}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch1}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch2}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch3}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch4}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch5}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch6}] -group [get_clocks {u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|rx_clkout|ch7}] -group [get_clocks {altera_reserved_tck}]

 

To explain, the script above should set false path below all node groups, thereby removes all timing violations.

Wondering why would the script works in the timing analyzer GUI console but not working (ignored) in the sdc file during compilation? Thanks.

 

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SyafieqS
Employee
2,478 Views

Hi Sun,


Try to remove and add again the script and compile it to see if it reflect any changes


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Winston_Sun
Beginner
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Hi, I removed and re-add the sdc file to the project (in Project -> Addd/Remove Files in Project...) and compiled, but still shows all the clocks and signals in the sdc file are ignored.

warning examples:

Warning (332174): Ignored filter at intel_j204c_ed_rx_tx.sdc(42): u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|tx_clkout|ch0 could not be matched with a clock File: /nobackup/wsun2/jesd204c_remove_addr_concat/ADI_SPI_JESD204C_Nios_Styx_test_design/ADI_SPI_JESD204C_TX_design/hardware/ed/rtl/du/intel_j204c_ed_rx_tx.sdc Line: 42

Warning (332174): Ignored filter at intel_j204c_ed_rx_tx.sdc(42): u_j204c_rx_tx_ss|core_pll|core_pll_clk_1x could not be matched with a clock File: /nobackup/wsun2/jesd204c_remove_addr_concat/ADI_SPI_JESD204C_Nios_Styx_test_design/ADI_SPI_JESD204C_TX_design/hardware/ed/rtl/du/intel_j204c_ed_rx_tx.sdc Line: 42

 

The top qsys sdc file, intel_j204c_ed_rx_tx.sdc, is shown in qsf file as 

set_global_assignment -name SDC_FILE ../rtl/du/intel_j204c_ed_rx_tx.sdc

 

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SyafieqS
Employee
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Hi Sun,


Could you attached you qar here I try to replicate the issue. If this a bug, I will file ticket to developer. If the the desing is PnC, you can response to my email and attach it there.

What version of Quartus you are using?




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Winston_Sun
Beginner
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Hi Syafieq, I've sent the email with qar attached. The project version is QPro v20.4 (I’ve also tried QPro 20.2 before as well, but it gives the same warnings and timing violations). Please note that this design is based on intel’s JESD204C example design. All I modified is to replace the single JESD204C IP block in the intel example design with three separate JESD204C IP blocks (Duplex PHY + Simplex TX MAC + Simplex RX MAC). Also, I noticed that the JESD204C IP’s sdc files in the synth folder (generated by intel during compilation) has the same warnings, ignoring filter signals in the sdc.

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SyafieqS
Employee
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Hi Sun,


I just looked at the email. I'm checking the design now and will get back to you.


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SyafieqS
Employee
2,378 Views

Hi Sun,


Btw, have you tried the origin design, did Quartus ignored the constraint as well? or occur only when you replace the single JESD204C IP block in the intel example design with three separate JESD204C IP blocks (Duplex PHY + Simplex TX MAC + Simplex RX MAC) ? Let me know this as well.


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SyafieqS
Employee
2,372 Views

Hello Sun,


I can reproduce the issue with latest version as well. Seem this issue look to me like a bug. I am checking this with engineering team for further debug. Will let you know any update on this.


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SyafieqS
Employee
2,237 Views

Hi Sun,


Apologize for the late response. Can you check the SDC order of the node signal. This could be due to constraint order is specified latter. Make sure the node is not specify latter in the sdc part as this will not take any effect during compilation. 





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Winston_Sun
Beginner
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Hi, 

 

yes, that is the problem. What is the general rules for the sdc constraint files order in the qsf file?

 

Thanks,

Winston

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SyafieqS
Employee
2,165 Views

Hi Sun,


The order of your file in setting -->general--> files should be sdc at the top of instead of sdc at the latter part.

Can you check if KDB below is applicable?

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2021/incorrect-sdc-compilation-order-in-quartus-20-4-during-flat-flow.html


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SyafieqS
Employee
2,075 Views

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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