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SDI Megacore on Stratix4 GX devkit. Mismatch pinnames in UG with actual device.

Honored Contributor II



I'm trying to follow the SDI core on an S4 GX dev kit board. 

See also: http://www.altera.com/literature/ug/ug_sdi_ii.pdf 


Altera provide an example design S4GXSDI_AUDIO_TOP 


In this guide the apply a pin constraint on page A-7 


set_location_assignment PIN_99 -to sdi_rx  


However, the S4 GX has names starting with a letter and then a number. 

For example : The design has "sdi_rx_p" on PIN_L2. 


Anybody every encountered this mismatch in user guide versus design. 

Can I just use the PIN_L2 instead of PIN_99? 



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Honored Contributor II

Hi Kimberly, 


I rarely use the example designs as the "golden" reference for a kit, I always use the schematic (or at least confirm each pin in the golden reference with the schematic). 


I've attached my pin constraints file. Here's the SDI section from that file: 


# Video out clock control (p6,9 ) set pin(sdi_clk148_up) {PIN = AH12, IOSTD = "2.5 V", DRIVE = 12mA, SLEW = 0} set pin(sdi_clk148_dn) {PIN = AH11, IOSTD = "2.5 V", DRIVE = 12mA, SLEW = 0} # Video out control set pin(sdi_tx_sd_hdN) {PIN = V29, IOSTD = "2.5 V", DRIVE = 12mA, SLEW = 0} # Video out set pin(sdi_tx) {PIN = K4, IOSTD = "1.4-V PCML"} set pin(sdi_tx(n)) {PIN = K3} # Video in set pin(sdi_rx) {PIN = L2, IOSTD = "1.4-V PCML"} set pin(sdi_rx(n)) {PIN = L1}  



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Can I just use the PIN_L2 instead of PIN_99? 


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Yes, pin 99 is wrong, pin L2 is correct. 



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