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Valued Contributor III
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SDRAM PLL phase adjustment DE2-70

I'm trying to incorporate the SDRAM into a simple nios system. Following the tutorial it says to have a PLL output a clock with a 3ns phase shift to account for delay with respect to the controller however it doesn't work and I get this error 

 

Verifying 00800000 ( 0%) 

Verify failed between address 0x800000 and 0x800697 

Leaving target processor paused 

 

Possible causes for the SREC verification failure: 

1. Not enough memory in your Nios II system to contain the SREC file. 

2. The locations in your SREC file do not correspond to a memory device. 

3. You may need a properly configured PLL to access the SDRAM or Flash memory. 

 

I looked at the SDRAM controller document to find the way to calculate the timing window and calculate the right phase shift 

-From the SDRAM datasheet(IS42S83200B) 

Toh= 2.7ns & Tdh= 1ns 

 

-From the classic time analyzer running with a 50Mhz clock no PLL 

Th_max= 1.512ns & Tco_min=5.07ns 

 

Read Lag = tOH(SDRAM) – tH_MAX(FPGA)= 1.188ns 

 

Read Lead= tCO_MIN(FPGA) – tDH(SDRAM)= 4.05ns 

 

Then my phase shift comes out to 2.862ns 

 

It still doesn't work, what might be my problem?? I've tried many combinations and tried both SDRAMs but still get the same error, help please!! 

 

Thanks
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Valued Contributor III
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--- Quote Start ---  

to have a PLL output a clock with a 3ns phase shift to account for delay with respect to the controller however it doesn't work and I get this error 

--- Quote End ---  

 

 

The clock for the SDRAM should LEAD with respect to the FPGA clock. The phase shift should be NEGATIVE: -3ns . 

 

Hope this helps...
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Valued Contributor III
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Thanks, Sorry I meant "-3ns' as well, it doesn't work and i have tried different values like -2.5 and -3.5... My calculated phase shift does come out positive so i don't know if i'm calculating it wrong or what

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