SDRAM problem

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

SDRAM problem

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Hi all.

I am using de-2 board.

I am trying to access the SDR sdram on board without using a nios system(but still using a SOPC builder).

Tutorial(s) provided by altera says to use a -3 ns delay in order to have a correct timing with the controller; but even if I drive the sdram controller with a -3ns @50MHz clock, ito doesn't work.

ow, the question is.. How can I find the right delays by own?

I've tryied to run timing analysis but I wasn't still able to find the right timing.

It'so frustrating.

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