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Altera_Forum
Honored Contributor I
1,133 Views

SDRAM rzqin pin on Arria V starter kit

Hello Alteraforums 

 

I'm trying to get the SDRAM on my Arria V starter kit working. I have set up the module in my qsys design, and have exported the appropriate conduits. 

 

There is an input called oct rzqin. After some searching, I have determined that this needs to be connected to a dedicated RZQIN pin. I've looked through the reference manual for the device, but there doesn't seem to be a pin for rzqin. the closest I find is this: 

https://alteraforum.com/forum/attachment.php?attachmentid=15178&stc=1  

 

If I don't connect the oct rzqin to something, I get compile errors.  

 

What do I connect this to?
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5 Replies
Altera_Forum
Honored Contributor I
92 Views

From that table, L8 is the RZQ pin.

Altera_Forum
Honored Contributor I
92 Views

I should have included the top of the table. 

 

That column is the 'Board Reference' Column. The pin column is the third column 

https://alteraforum.com/forum/attachment.php?attachmentid=15179&stc=1  

 

Taken from page 2-41 of this document: 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_avgx_starter_bo...
Altera_Forum
Honored Contributor I
92 Views

I'm not sure why the pin is not shown there, but if I recall correctly, you should be running a pin_assignments.tcl script after creating the memory IP (assuming you're using the hard controller) that makes fixed assignments like this for you. You can, of course, check the pin table for the device to see which pin is the dedicated RZQ pin for the hard interface you are using. 

 

You could also try opening one of the example designs for the board from the "kit installation" download (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-arria-v-starter.html) and use that as a basis for your design.
Altera_Forum
Honored Contributor I
92 Views

Using a reference design, I determined that PIN_E32 should be the right one 

 

I try to compile, but when the fitter runs, I get 1400 errors! 

 

here's some examples: 

Error (174068): Output buffer atom "nios_system:inst2|nios_system_sdram:sdram|nios_system_sdram_p0:p0|nios_system_sdram_p0_memphy:umemphy|nios_system_sdram_p0_new_io_pads:uio_pads|nios_system_sdram_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|extra_output_pad_gen.obuf_1" has port "SERIESTERMINATIONCONTROL" connected, but does not use calibrated on-chip termination Error (174068): Output buffer atom "nios_system:inst2|nios_system_sdram:sdram|nios_system_sdram_p0:p0|nios_system_sdram_p0_memphy:umemphy|nios_system_sdram_p0_new_io_pads:uio_pads|nios_system_sdram_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|extra_output_pad_gen.obuf_1" has port "PARALLELTERMINATIONCONTROL" connected, but does not use calibrated on-chip termination Error (174068): Output buffer atom "nios_system:inst2|nios_system_sdram:sdram|nios_system_sdram_p0:p0|nios_system_sdram_p0_memphy:umemphy|nios_system_sdram_p0_new_io_pads:uio_pads|nios_system_sdram_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen.data_out" has port "SERIESTERMINATIONCONTROL" connected, but does not use calibrated on-chip termination Error (174068): Output buffer atom "nios_system:inst2|nios_system_sdram:sdram|nios_system_sdram_p0:p0|nios_system_sdram_p0_memphy:umemphy|nios_system_sdram_p0_new_io_pads:uio_pads|nios_system_sdram_p0_altdqdqs:dq_ddio.ubidir_dq_dqs|altdq_dqs2_acv_arriav:altdq_dqs2_inst|pad_gen.data_out" has port "PARALLELTERMINATIONCONTROL" connected, but does not use calibrated on-chip termination Error (174052): I/O "SDRAM_DQ" has dynamic termination control connected, but does not use parallel termination
Altera_Forum
Honored Contributor I
92 Views

Did you run the pin_assignments.tcl script, as suggested by sstrell? (Tools menu, TCL scripts, and find the pin_assignments script in the SDRAM controller IP). It should fix the I/O standard and termination issues.

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