I have an Altera Board with 88E1111 on it connecting to FPGA via LVDS I/Os. I have an SGMII core under verification. I did manage to run the Auto-nego successfully once. Then after that I have no idea what changes make the thing not work any more. The Phy keeps sending out: BC 42 00 00, BC 5B 00 00 ... ==> my SGMII core is therefore stuck at Ability Detect I've read the register 17 page 1 for the status, value = A010 which translates to: - Fiber link not up - Fiber energy not detected Another problem is i don't have a scope to check for the signal. :( Any advice? Any PHY register to read to find out more what's going on? Any setting to the LVDS TX at the FPGA side? Thanks a lot! I'm really afraid that the LVDS receiver at the PHY is blown up :(.