SLVS signal pin feeding Deserializer

[MamaSaru]

Hi,

I can’t find Intel FPGA device like below:

1. Can receive 1.6Gbps SLVS differential signals.
2. These SLVS inputs feed each source synchronous Deserializer.
3. Number of SLVS inputs is 60 pair, preferable 120 pair.

The Center voltage of SLVS is lowered to 0.2V in it’s specification.

Because of this, Arria 10 or Cyclone 10 GX could not handle the speed of 1.6Gbps.

Do you have any idea to realize my needs?

Should I use other vendor’s FPGA?

Masaru

[MamaSaru]

​sorry for posting improper community.

I will repost to programable device community.

[YuanLi_S_Intel]

Hi Masaru, Apologize that the SLVS I/O standard is only available in MAX 10. For Arria 10 and Cyclone 10 GX, you might need to choose the different pair in which the electrical specification is matching the input SLVS signal. Regards, YL