FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

SPI TIMING CONSTRAINTS

hsyn
Beginner
956 Views

Hello,

How can I constraint spi signals shows on below?

I didn't understand how I can write a sdc file for this scenario.

0 Kudos
3 Replies
hsyn
Beginner
941 Views

How can i determine these values? (test.png)

0 Kudos
Kenny_Tan
Moderator
925 Views

Hi, you may refer to https://community.intel.com/t5/FPGA-Wiki/Constrain-SPI-Core/ta-p/735358


It had example datasheet over there. You can take a look and follow.


0 Kudos
Kenny_Tan
Moderator
895 Views

We do not receive any response from you to the previous question/reply/answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


0 Kudos
Reply