FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5283 Discussions

SRAM Corruption is MAX V CPLD

MHamz1
Beginner
437 Views

Hi,

I am facing an issue in MAX V CPLD, when the voltage rail is increased slowly from 0 to 1.8 V with minor fluctuations, the CPLD logic behaves abnormally, like some part works and some part does not.

Majorly according to my observation the Variable used for creating state machines are getting corrupted.

Kindly suggest a suitable fix or workaround for this issue, can the SRAM be loaded again? or how can it be handles in HDL efficiently

0 Kudos
1 Reply
ShafiqY_Intel
Employee
139 Views

Hi MHamz1,

 

When you configure MAX V CPLD, can you try to check on Configuration Pins (nConfig, nStatus, Conf_done and Init_done) ?

 

Thanks.

Reply