Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,092 Views

SRAM K1B3216B2E on Cyclone III Development Kit

dear sopc experts, 

 

has anyone used the 2 x 32mbit sram K1B3216B2E on altera cyclone III development kit or altera stratix III development kit? 

 

my problem: i instantiated a sopc with an tristate bridge, where my sram-interface is the mm-slave. my sram-interface component is associated with the SRAMInterface.vhd. 

 

can anybody tell me, what i've done wrong? because it doesn't work! 

 

thanks in advance! 

 

reto
0 Kudos
33 Replies
Altera_Forum
Honored Contributor I
102 Views

Hi, 

 

I had a quick look at your code. 

 

A possible pitfall is the bidirectional assignment... here is how it could go wrong: 

 

if B1 and B2 are two bidirectional nodes(inout ports) then any wiring assignment must take into account double driving.  

for example: 

B1 <= B2; 

 

doesn't mean they are wired up contrary to popular belief. It means B2 is driving B1 but not the other way round 

 

hence you must also add: 

B2 <= B1; 

You will need appropriate mux to avoid multiple drivers 

 

Kaz
Altera_Forum
Honored Contributor I
102 Views

thank you for your quick reply!!! 

 

no, i tried it. that generates an synthesis error: 

 

Error (10666): Bidirectional ports "AvS1DataxDZIO[31]" and "SramDataxDZIO[31]" at SRAMInterface.vhd(36) directly or indirectly feed each other 

 

regards, 

reto
Altera_Forum
Honored Contributor I
102 Views

It remains crucial that you drive each of your outputs. You can't just drive one of your two inout ports. 

 

It is a matter of the design platform to find out how to drive each output. 

You may need to define who is driving who through a mux. 

In my project(not a dev board). I interfaced with sdram and flash with bidirctional buses and used double assignment without problem(Quartus 7.2). 

 

The error may be due to occurence of mutiple drivers on a node which is not allowed(a node must have one driver at any given time). 

 

Kaz
Altera_Forum
Honored Contributor I
102 Views

May be a quicker way is to redefine the avalon inout as separate in/out then wire up to the bidirectional pin in two assignments. Alternatively use port map which look after the wiring. 

 

kaz
Altera_Forum
Honored Contributor I
102 Views

hi kaz 

 

i think it should do, if i only connect the bidir-signals with one <= statement. but i will have a go... 

 

thank you! 

reto
Altera_Forum
Honored Contributor I
102 Views

so, it still doesn't work, but i am one step further. it's not necessary to connect the tri-state data lines through my custom sopc component, i can take directly the ones from the tri-state bridge... 

 

can anybody tell me, whats going wrong, i attached my .vhd (custom component in sopc builder)... i connected address bit a[0] with a[2] from avalon-mm master, hope this is correct, due to 32-bit data (not 8-bit) 

 

thanks in advance for any assistance! 

reto
Altera_Forum
Honored Contributor I
102 Views

Hi, 

 

First: you should discard two address LSBs, not three. 

Second: you have commented out address and data lines?? 

third: why using this complex cascade of two tristates ? 

 

If all you need is just do something? for the "wait" signal from sram then why not just port map nios avalon directly to your top project except for doing that something, I don't see any need for this module in the first place. 

 

Why do you do that something in hardware, why not leave it for software as the software is supposed to read/write to sram. 

 

kaz
Altera_Forum
Honored Contributor I
102 Views

first: i discard two LSB's --> address line of development board beginns with a1...a21 

second: i shared address lines with other peripherals --> setting in tri-state bridge of sopc builder 

third: this cascade is really stupid, i deleted it ;-) 

 

your are right, i don't need such a component with a vhdl-file, i built now a component with only one _hw.tcl file --> see attachment 

 

IT STILL DOESN'T WORK and i don't know why? 

 

THANK YOU very much for any help! 

Reto
Altera_Forum
Honored Contributor I
102 Views

I am not sure about which address you mean starts with a(1) rather than  

a(0). You say the "peripheral", it sounds you mean sram address.  

 

You need to discard 2 bits of nios avalon address bus i.e. connect nios avalon address line(2,3,...etc) to all of your sram address lines. But in your previous vhdl, you connect nios address lines(3,4,...etc) to sram and this is wrong. 

 

I am not good at TCL. If you upload your nios entity, top project entity and your instantiation then I may be helpful 

 

kaz
Altera_Forum
Honored Contributor I
102 Views

here i am with my top-level entity (.bdf) and sopc-system 

 

thank you kaz for your quick help! 

reto
Altera_Forum
Honored Contributor I
102 Views

From what I can read, you don't have any hold or wait states for write access. 

You can try this one, that I used on the board a while ago. It is rather slow with some conservative timing figures, but it should work.
Altera_Forum
Honored Contributor I
102 Views

Hi Reto, 

 

I had a look at the sopc schematic. 

 

I believe your addressing is not right(assuming altera haven't change the tristate bridge addressing scheme from what I had used before). 

 

You have grounded address bit(0) then you discard address bits(2:1). This means you are discarding 3 bits off avalon address. I will not ground any address bit and then discard bits(1:0). 

 

I am not familiar with dev boards, so you must get other people's advice regarding other signals. 

 

Kaz
Altera_Forum
Honored Contributor I
102 Views

TO Daixiwen: thank you for your example! Unfortunately, it doesn't work, when i run my nios II project (hello world) on it. nios ide can validate the sram, but the program doesn't run properly (my uart doesn't send any characters...) 

 

did you set 'data' and 'address' as shared signals in tristate_bridge (sopc builder)? 

 

 

 

TO kaz: i grounded address bit 0, because the sram-address-port addressSRAM(0) is connected with adressSFBus(1) and addressSRAM(20) is connected with adressSFBus(21). so i only discard addressSOPC(0:1). i hope it is clear now... difficult to explain for me without a picture. 

 

 

 

Altera wrote me this: 

 

When you create a SOPC component based on HDL file, you can’t use tri-state MM slave interface. sram K1B3216B2E can be used as popular sram. I have attached the component, you can use it. If you are using the standard example shipped with the kit, please check the pin assignments of fsd16~fsd31. There are several errors please correct them according the reference manual. 

 

The option bits address is 0x3fe0000 instead of 0x380000. Page 1 start address is 0x380000. Please refer to the attached screen shot to program the flash. 

 

 

 

reto's opinion and questions: 

 

- to the pin assignment: does anybody know where i can found the correct pinout? i checkt it several times with schematic and reference guide, but didn't found any error. 

 

- i can't set options address on 0x03fe0000, because its an cfi_64MB, not a cfi_512MB, so address range is smaller than 0x03fe0000. what's the correct options address? 

 

 

thank you for any help, i'm loosing my patient bit by bit! 

reto
Altera_Forum
Honored Contributor I
102 Views

The only signals I have shared are data and address. I only had one bit to remove from the address bus (see attached picture), but it may be different than your system because I don't use the flash at all. 

If you used some of Altera's design example projects as a start, some data pins are not connected properly. See this message (http://www.alteraforum.com/forum/showthread.php?t=2609) and change your assignments accordingly, if required. 

I think that you should start with a very simple SOPC system, with only what's necessary for a memory test (CPU, big on-chip memory, SRAM, JTAG UART, System ID). Then compile the memory test example, run it from the on-chip memory, and ask it to test the SRAM. Then you should be able to see if it fails completely or partially. If you still can't understand what's going on, use a SignalTap probe to check the SRAM signals.
Altera_Forum
Honored Contributor I
102 Views

Hi Daixiwen, 

 

thank you for your picture. when i connect your sram component like this, nios II ide load the firmware correct (.text, .rodata, .rwdata) into the sram and verify it successfully. 

 

but if i run the programm, it doesn't work (hello world to jtag-uart). did you set some timing constraints for output pins? e.g. 1ns clock to output delay (in assignment editor of quartus II)? 

 

thank you very much for your help! 

 

regards, 

reto
Altera_Forum
Honored Contributor I
102 Views

I've put these constraints, but I'm not sure they are necessary, as it is an asynchronous interface and the setup and hold times on the SOPC component are larger than the actual requirements of the SRAM. 

create_clock -name {clkin_50} -period 20 -waveform { 0 10 } set_input_delay -clock clkin_50 -max 15 }] set_input_delay -clock clkin_50 -min 0 }] set_output_delay -clock clkin_50 -max 15 fsa sram_ben sram_csn sram_advn sram_oen sram_wen sram_psn sram_clk}] set_output_delay -clock clkin_50 -min -4 fsa sram_ben sram_csn sram_advn sram_oen sram_wen sram_psn sram_clk}] 

Downloading the software in SRAM through the IDE doesn't fully test the memory. Have you tried to compile the "memory test" design example in on-chip RAM, and have it test the SRAM? 

Does your "hello word" program work from on-chip memory?
Altera_Forum
Honored Contributor I
102 Views

Have you tried to compile the "memory test" design example in on-chip RAM, and have it test the SRAM? 

 

--> yes, it's strange. the memory test passed every bit, byte and half-word access! 

 

 

Does your "hello word" program work from on-chip memory? 

 

--> yes, my hello world works from on-chip ram and sdram, but not from my sram... 

 

 

next step will be: setting your timing constraints! 

 

!!!!!!!!!!!!!!!!THANKS A LOT!!!!!!!!!!!!!!!!!!!!! 

 

Regards, 

Reto
Altera_Forum
Honored Contributor I
102 Views

Here the component which works with my board. It's quit slowly, but reliable :) .  

 

 

!!! If anybody can speed it a little up, please let me know !!! 

 

 

Thanks to you Daixiwen and kaz!!! 

 

Reto
Altera_Forum
Honored Contributor I
102 Views

Unfortunately the SRAM is used in asynchronous mode, and can't be used a lot faster than this. I don't understand why your system doesn't work with my timings though, this is very strange... 

If you want to speed up the interface, you would need to write a controller in VHDL or Verilog, to handle burst transfers. Unfortunately burst transfers can't be used with tristate bridges AFAIK, so this means you wouldn't be able to use the flash at the same time any more...
Altera_Forum
Honored Contributor I
11 Views

Hi, 

 

Can you please let me know how fast is the SRAM component. What is the the performance? 

 

Regards 

Foram
Reply