FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5360 Discussions

SRAM READ and WRITE Cycle Of External SRAM Cyclone III Starter Kit

Altera_Forum
Honored Contributor II
832 Views

Hello, 

 

I want to write an Sram controller (Read Cycle followed by a Write cycle) on Cyclone III starter kit Board. I have an external Sram (IS61LPS25632A).  

I have the following Signals to be controlled: Sram_ce1_n (active low), Sram_we_n (I suppose low for write, and high for read), (Sram_be_n0, Sram_be_n1,Sram_be_n2,Sram_be_n2 I set them to zero 

because I want to access all bytes), Sram_adsc_n (I set it to zero) and the clock Sram_clk (I put the rising edge in the middle of the cycle), Sram_oe_n (I set it to low, should i toggle it ???). The timings of the data sheet of the Sram is for me not clear, I don't nee burst access, just I want to read one address radr1 and then write another adress wadr1 and then read again radr2 and write wadr2 and so on, please can somebody provide a timing diagramm or a piece of RTL code ?  

 

thanks a lot  

 

regards Chahid
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
120 Views

mark.i have the same problem.

Reply