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Altera_Forum
Honored Contributor I
1,119 Views

SSRAM Chip/Clock and Flash Clock on Cyclone III Starter Kit

Dear all, I am using the cyclone III Starter kit example: cycloneIII_3c25_start_niosII_standard project, and run into a few questions, could you help me?  

 

1. why the SOPC using Cypress cy7c1380c SSRAM controller, while the actual chip is IS61LPS25636A ? are they replaceable? 

 

2.The clock to SOPC cypress cy7c1380C is system_clk, the clock out to the chip of IS61LPS25636A is ssram_clk, they are different clock and have a phase difference of 146.88 dg set by DLL, why they have this phase difference? 

 

3. The SOPC flash interface has clock, but there is no clock out to the flash chip, why? the flash chip doesn't need clock? but the schematics of flash chip have a clock input. 

 

4. the flash_ssram_a[0] doesn't use and be assigned to any pin, how they get rid of it in the Pin Planner? In my project, I try to get rid of it, but in vain. 

 

Thank you very much!
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3 Replies
Altera_Forum
Honored Contributor I
60 Views

That's all my questions too

Altera_Forum
Honored Contributor I
60 Views

Hi, I have a simple question regarding the SSRAM Nios 2 core. How did you generate a clock that was synchronous with the data bus. The Nios 2 module doesn't provide a clock, why no clock? I'm trying to use it on a cyclone 3 starter kit without much success 

 

Thanks
Altera_Forum
Honored Contributor I
60 Views

The clock used for the SSRAM data bus is the clock that you defined in SOPC builder for the SSRAM component. Just use the same clock for the external interface.

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