I am trying to read a bunch of data from SSRAM (IS61LPS25636A)) on Cyclone III, which is 256k*32 bit in size. However, from the board manual, there are 32 data bits, 21 address bit (should be 18 bits for 256k), Does anybody know this problem? what are the additional three pins?
There is no problem. A20 and A19 are marked as NC (not connected) in the schematic. A18 is also without function, as the ISSI datasheet clarifies. They are reserved for same package, higher capacity parts.
--- Quote Start --- There is no problem. A20 and A19 are marked as NC (not connected) in the schematic. A18 is also without function, as the ISSI datasheet clarifies. They are reserved for same package, higher capacity parts. --- Quote End --- FPGA manual http://www.issi.com/pdf/61vps_lps25636a_51218a.pdf and the manual for this board here http://www.altera.com/literature/ug/ug_ciii_starter_kit.pdf (http://www.altera.com/literature/man...rter_board.pdf) Hi, Do you mean A20 A21, A22 As shown above in the manual? I can not find information about "They are reserved for same package, higher capacity parts." Did you successfully read data from it using verilog/VHDL? Thanks.
--- Quote Start --- Do you mean A20 A21, A22. --- Quote End --- Yes, the pin names are different between schematic and reference manual. The pins are functionless and don't need to be connected to your design.
I tried to use the following code to read a set of data from SSRAM, but found I can only get the very first data in address 18'b0; can not read others even I changes the address.Can anybody help about this? Thanks. `timescale 1ns / 1ps module mem_read( ssram_clk, clk, reset_n, ssram_adsc_n, ssram_bw_n, ssram_bwe_n, ssram_ce_n, flash_ssram_a, flash_ssram_d, ssram_oe_n, test_led ); input ssram_clk; input clk; input reset_n; output wire ssram_adsc_n; output wire [3:0] ssram_bw_n; output wire ssram_bwe_n; output wire ssram_ce_n; output wire [19:2] flash_ssram_a; input [31: 0] flash_ssram_d; output reg ssram_oe_n; output wire [3:0] test_led; assign ssram_adsc_n=1'b1; assign ssram_bw_n=4'b1111; assign ssram_bwe_n=1'b1; assign ssram_ce_n=1'b0; // assign flash_ssram_a=counter1; // assign ssram_oe_n=1'b0; reg [1:0] counter; always@(posedge ssram_clk, posedge reset_n) begin if (reset_n) counter <=2'b00; else if (counter1==18'b111111111111111111) counter <=2'b00; else if (counter==2'b11) counter <=2'b01; else counter <= counter + 2'b1; end //counter reg [17:0] counter1; always@(posedge clk, posedge reset_n) begin if (reset_n) begin counter1 <= 18'b111111111111111111; end else if (counter1==18'b111111111111111111) counter1<=18'b000000000000000000; else begin counter1<=counter1+18'b1; end end assign test_led=reset_n; assign flash_ssram_a =counter1; always @(negedge ssram_clk, posedge reset_n) begin if (reset_n) begin ssram_oe_n <=1'b1; end else if (counter1==18'b111111111111111111) begin ssram_oe_n <=1'b1; end else if (counter==2'b01||counter==2'b11) begin ssram_oe_n <= 1'b1; end else if (counter==2'b10) begin ssram_oe_n <= 1'b0; end else ; end endmodule
The name reset_n suggests that your reset signal is active low, but in your code you are resetting your system when it is 1... are you sure you aern't keeping yr design in permanent reset?Are the clocks clk and ssram_clk related? You are crossing from one domain to the other without any protection and it could cause problems.
Yes, I took care of the reset_n, and used a inverter before reset_n on the button on FPGA.clk and ssram_clk are related as they are the pll outs from single master clk(50MHz). Thanks. I can send you all the project source if you are interested. It's about 20 M. My msn:email@example.com
Try to put everything on a rising edge of the clock, it will make it easier to see what is going on.To perform a read you also need to put a 0 on either /ADSP or /ADSC to load the address into the memory.
I don't have access to quartus during this week so it would be difficult for me to check your project.On the screenshot that you show, ADSC_n is 1 so the address is never loaded by the SRAM.
Yes, I also thought ADSC should be 0, hence the ADSC_n should be 1. Am I right? The same thing for other control signal, since there is a _n following them. thanks
The waveforms that you have now look correct. Are you sure that those signals are connected to the correct pins outside the FPGA? Is the flash disabled?It may sound stupid but are you sure that the first addresses in the SRAM hold different values?
I checked the values in the first several addresses, they are differentHere I attached new signals. I put the values as FFFFFFFF, 05060708h,090A0B0Ch, 0D0E0F10h, 11121314h,....in the first addresses of the ssram memory. I still can not get the different values at the rising edge of clk_test. But it seems near to succeed. I also checked and attached the pin assignment. what's the flash disabled? I have no idea about this.
The SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try.
The SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.I tried , but it did not work as attached How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. I used the control pannel to write valules manually, which is a integrated software in quartus. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. I attached the schematics for this project, you can see that the pins here are only for output monitor. The signal source come from 50MHz source via pll. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try. I tried, it does not work, as attched. Did you successful read data from ssram before? Thanks
Yes I have a design that connects an avalon slave bus to a SSRAM, and can read and write.When you wrote the values in the SSRAM, was it with a different configuration in the FPGA? Your design isn't able to write to the SSRAM. I didn't find the schematics in your attachments.
Your document is difficult to read, the resolution is too low.I didn't find any clock output to the ssram clock (pin A2). Where is it? I can have a look at your project this week-end. My email address can't receive 20M, but you can use a service such as http://demo.ovh.org/ and send me the link in a PM.