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Sushmita
Beginner
203 Views

Should read request signal in avalon interface be a continously high signal or just a pulse?

Hi,

 

I want to use avalon interface to read the data from DDR to BRAM with a burst size of 512, bit interface is 64. Currently i am sending the read request as a pulse. But i am not sure if it is the correct way. My rtl stops at some point when i run it on FPGA .

 

Can someone specify if the READ REQUEST is a pulse or continuous signal?

 

 

Thanks

SBilg

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7 Replies
sstrell
Honored Contributor II
58 Views

There is no "read request" signal in Avalon. If you are saying that you are reading from an Avalon slave, as a master, you must honor the waitrequest signal. You can issue a read command to the slave, but you must hold the command active until one clock cycle after waitrequest goes low (unless there's some additional latency parameters set by the slave) at which point the readdata should be available.

 

See the Avalon spec for details:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

 

#iwork4intel

Sushmita
Beginner
58 Views

Hi sstrell,

 

Yes, i want to read as a master. I am using the signal WAITREQUEST_N. When i run the module on FPGA, the WAITREQUEST_N is always high, irrespective of whether i am issuing a read command or not. I am using a single master.Even In this case should my module be WAITREQUEST_N dependent?

 

Thank you for your reply.

KennyT_Intel
Moderator
58 Views

Your wait request need to be deassert in the slave itself. without deassert on the slave, you cannot do anythings.

 

Unless you are using fixed wait states, your wait request need to be deassert. Page 26 base on the link above.

 

 

KennyT_Intel
Moderator
58 Views

additionally, you can refer to the above link page 21 for the waveforms and explanation.

KennyT_Intel
Moderator
58 Views

Any further queries?

Sushmita
Beginner
58 Views

Hi,

What happens to the wait request while the data is being sent from the slave side? Does it remain low​ the whole time until entire transaction is completed?

KennyT_Intel
Moderator
58 Views

 When the slave asserts waitrequest, the transfer is delayed. While waitrequest is asserted, the address and other control signals are held constant. Transfers complete on the rising edge of the first clk after the slave interface deasserts waitrequest.

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