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Should -ve *setup* slack in Slow_900mV_0C model also show up in Slow_900mV_100C model?


I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900V_100C model. I would think the process part of the model is likely the same in the two timing models, then I would expect the circuit to run slower at higher temp and same voltage. Then why do those paths not see any setup violations?

Thank you.

Best regards,

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Hello SP, I am think temperature affects the transistor speed by changing the characteristics of the silicon material (Threshold voltage), leakage current and electron mobility. As Temperature increases , delay of the transistor can i) Decrease due to decrease in threshold voltage ii) Increase due to decrease in the mobility. Hence at high temp delay mainly because of mobility and at low temperature delay mainly because of decrease in transistor gate threshold voltage. Essentially , Low temperature is consider as the worst case (i.e threshold voltage variation) compare to high temperature. Intel timing model is accurate enough to differentiate. Can I ask how much negative slack you get in set up time at 0C ? can you kindly let me know how i can help you further ? Thank you, Regards, Sree
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