SignalTap Cyclone V query

[dboyle]

Hello,

Newbie query but any pointers in how to do this would be much appreciated.

I am trying to debug FPGA logic when SW is running on the ARM using. The steps I take are as follows;

1. I generate a *.sof with the SignalTap nodes.

2. Create an image file (SW included).

3.Download to the platform. 

4. Boot the platform.

The platform boots as expected however I am unable to get the Signal Tap Logic Analyzer to acquire the target nodes after a "Scan Chain" (the chain is recognised).

Am I going about this wrong way?

Any suggestions would be much appreciated.

Kind regards.

Dominic

[sstrell]

It depends on if you want Signal Tap triggering to cause a software break to occur or if you want a software breakpoint to cause Signal Tap to trigger.  Use the Trigger In and Trigger out options in your .stp file to configure this.

Or are you saying Signal Tap is just running standalone and it's not triggering?  Then check your trigger conditions and make sure they are actually occurring in your hardware design.

[dboyle]

Hi sstrell,

I haven't got that far.

My question is how I get the Signal Tap tool to acquire the nodes via JTAG when booting the SOC from Memory (image file) rather than download the SOF file via JTAG as the tool seems to explicitly require?

Regards.

Dominic

[sstrell]

So you're booting the HPS and having it program the FPGA (HPS boot first flow) which includes Signal Tap.

Then when you try to access the Signal Tap instance in the .stp file, you are not getting a status of "Ready to acquire" even though the device shows up in the JTAG Chain Configuration section of the window?  The tool does not require you to manually program the device.  As long as the device is programmed with a design that includes a Signal Tap instance (and your .stp file settings are compatible with that instance), it should work over JTAG.

As a test, I'd try manually programming just the programming file to the FPGA (not booting the HPS) and verifying that Signal Tap works that way.  If it does, can you verify that the HPS is successfully configuring the FPGA itself with the same image?

[RichardTanSY_Intel]

Hi @dboyle 

May I know does the suggestion from sstrell helps? 

Do you need further help regarding to this case? 

Thanks.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[RichardTanSY_Intel]

Hi @dboyle 

I have yet to receive any response from you but I assumed that you have found a solution to your issue. 
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.