Simple DMA Example - Acknowledge level-sensitive Interrupt

[Altera_Forum]

Hello, 

 I was wondering whether anyone can point me in the right direction helping me figure out to get a simple DMA transfer from the SOPC on-chip memory to the Root Complex memory going. I'm specifically having troubles with the interrupt assertion.  I'm using the "SOPC Builder PCI Express Design with GUI Interface" (AN 532) modified to run on the Altera Arria GX Development Board. The demo application (Altera PCI Express SOPC Demo) that goes along with the demo design works just fine. I'm able to kick-off all kinds of transfers.   Now I'm trying to actually get into the SW development itself, using the "Jungo PCI.NET Sample" and the "Jungo Altera Diag" examples as starting points.  Using the "Jungo PCI.NET Sample" for setting up the DMA engine for a transfer from the SOPC on-chip memory to the host through the SOPC Tx Interface basically crashes my systems by means of a BSOD after setting the number of bytes to be transferred (which should basically kick-off the DMA process). After going through the source code of the "Jungo Altera Diag" I found the following comment in altera_diag.c:  printf ("WARNING!!!\n");  printf ("----------\n");  printf ("Your hardware has level sensitive interrupts.\n");  printf ("You must modify the source code of ALTERA_IntEnable(), in the file altera_lib.c,\n");  printf ("to acknowledge the interrupt before enabling interrupts.\n");  printf ("Without this modification, your PC will HANG upon interrupt!\n");  printf ("\n");  I do understand what it means (I guess) but really have no idea which register needs to be written to in order to acknowledge the interrupt. I believe that what's happening is that the interrupt stays asserted after the DMA transfer and the PC just cannot handle this overload.  My understanding of the process is this:  1. DMA Engine gets setup with source & destination address and control information (in this case from Root Complex through BAR2) 2. DMA Status bits are cleared (DONE cleared from potentially previous transfer) 3. Transfer length is written to the respective DMA register, which kicks-off the transfer 4. DMA reads (in this case) from on-chip memory and sends write requests to Root Complex via PCIe interface 5. Root complex buffers received data in respective memory space addressed by BAR2 6. A PCIe interrupt is asserted (source DMA?), signaling the completion of the DMA transfer 7. The Root Complex is expected to acknowledge the DMA transfer back to the Requester by means of clearing a bit in a register (or reading a register?) 8. The Root Complex reads the buffered data for further processing  I apologize if that's more related to the fundamentals of the PCI Express Protocol / Architecture. I was just thinking to post this question while waiting for my book on this technology to come in.  Any hints especially regarding SW are much appreciated. By the way: Does anyone have an idea why Altera does not release the source code of their demo apps?  Thanks, Steffen