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FPGA Evaluation and Development Kits

Simulation LPM_ADD_SUB

Savino
Beginner
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Good morning, 'm trying to simulate a simple three-bit adder with 1 but as soon as I launch ModelSIM and force the input signal to 000 for example, the output signal remains in z state. I also tried to input a clock signal but the output signal always remains in z state. How can I solve this? I expected that, whether forcing the input variable to a value or not, the output variable should increment its value by 1. Attached the drawing I am using.

Any Help?

LPM_ADD_SUB.png

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Savino
Beginner
162 Views

sorry, the right figure is this

LPM_ADD_SUB.png

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