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Altera_Forum
Honored Contributor I
768 Views

Simulation PCIe Cyclone IV

hI; 

 

Please I have a problem with the simulation relating the DMA test as follow: 

 

# INFO: 34104 ns Completed configuration of Endpoint BARs. # INFO: 35064 ns Starting Target Write/Read Test. # INFO: 35064 ns Target BAR = 0 # INFO: 35064 ns Length = 004096, Start Offset = 000000 # INFO: 47272 ns Target Write and Read compared okay! # INFO: 47272 ns Starting DMA Read/Write Test. # INFO: 47272 ns Setup BAR = 2 # INFO: 47272 ns Length = 004096, Start Offset = 000000 # FATAL: 400000 ns Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error!# FAILURE: Simulation stopped due to error!  

 

 

Please could anyone give me advice about?????????? 

I used the same steps as to designing Arri GX II but with Cyclone GX IV 

 

 

Regards
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5 Replies
Altera_Forum
Honored Contributor I
81 Views

Hi Henry, 

 

Thanks for your PM regarding this issue. I don't have permission to reply by PM as I have not posted enough messages. 

 

I never resolved this issue. A colleague tried a similar design with the licensed (rather than the Web) version of Quartus 9.1 and targeting Arria II GX rather than Cyclone IV GX and that simulated OK, but he was also not using ModelSim to run the simulation, so there may be other factors involved. 

 

Sorry I can't help this time. Please PM me if you find a solution. 

 

JB.
Altera_Forum
Honored Contributor I
81 Views

Ok  

 

I am working on Cyclone IV GX FPGA and I would let you informed if i get the solution......... 

Do you still work on FPGA Boards or not 

 

Regards
Altera_Forum
Honored Contributor I
81 Views

Henry wrote: Do you still work on FPGA Boards or not? 

 

We found a solution that met our requirements without solving the Quartus+ModelSim problems with Cyclone IV GX. However I would still like a solution to the problem you are having for future designs.  

 

We switched from Quartus V9.1 to V10.0 so we could use the "Completer-only single DWORD" Avalon PCIe peripheral mode option. We then removed the DMA from the design and access only 32 bit registers on the FPGA from the driver. This is fine for our design but clearly is not OK in designs where significant amounts of data are being transferred across the PCIe bus. 

 

JB.
Altera_Forum
Honored Contributor I
81 Views

Hi, 

 

Thanks for the advices.. 

We discuss today about how to remove the DMA to the Design.So if you have a picture of SOPC Design without DMA I would be thankfull. 

 

Regards,
Altera_Forum
Honored Contributor I
81 Views

Here's a simple design. 

 

JB.
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