Slack violation of "pcie_a10_hip|~CORE_CLK_OUT"

[JET60200]

Hello ,

On A10SOC KIT board, I compile PCIe_gen3x8-Avmm design example,  but Time Report show below critical warning ？ 

I wanto  understand what‘s this Critical Warning meaning’ is ? 

Does it mean the worst value of "Setup Time" ,between "altera_reserved_tck" to "pcie_a10_hip_0|~CORE_CLK_OUT" is "-0.002", and this negative -0.002 is not allowed.  right ? 

How to fix it ?  Thanks a lot

【

Info(332119): Slack End Point TNS Clock
Info(332119): ========= =================== =====================
Info(332119): -0.002 -0.004 u0|pcie_a10_hip_0|dut|wys~CORE_CLK_OUT
Info(332119): 0.246 0.000 u0|emif_0|emif_0_core_usr_clk
Info(332119): 0.539 0.000 u0|pcie_a10_hip_0|dut|tx_bonding_clocks[0]
Info(332119): 0.648 0.000 u0|emif_0|emif_0_phy_clk_l_0
Info(332119): 0.686 0.000 u0|emif_0|emif_0_phy_clk_l_2
Info(332119): 0.784 0.000 u0|emif_0|emif_0_phy_clk_l_1
Info(332119): 1.028 0.000 u0|pcie_a10_hip_0|dut|pld_clk
Info(332119): 2.197 0.000 u0|emif_0|emif_0_core_cal_master_clk
Info(332119): 3.658 0.000 u0|emif_0|emif_0_core_cal_slave_clk
Info(332119): 4.713 0.000 emif_0_pll_ref_clk
Info(332119): 11.949 0.000 altera_reserved_tck

】

[Kenny_Tan]

Yes, it should not be allowed. This happened usually you use a different version of Quartus Prime.

This clock used for signal tap. What you can try is use different seeds to close the timing since the value is small.

[Kenny_Tan]

Any update?

[Kenny_Tan]

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