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Slack violation of "pcie_a10_hip|~CORE_CLK_OUT"

JET60200
New Contributor I
212 Views

Hello ,

On A10SOC KIT board, I compile PCIe_gen3x8-Avmm design example,  but Time Report show below critical warning ? 

 

I wanto  understand what‘s this Critical Warning meaning’ is ? 

Does it mean the worst value of "Setup Time" ,between "altera_reserved_tck" to "pcie_a10_hip_0|~CORE_CLK_OUT" is "-0.002", and this negative -0.002 is not allowed.  right ? 

 

How to fix it ?  Thanks a lot

HIP_CoreCLK_VIO.png

 

Info(332119): Slack End Point TNS Clock
Info(332119): ========= =================== =====================
Info(332119): -0.002 -0.004 u0|pcie_a10_hip_0|dut|wys~CORE_CLK_OUT
Info(332119): 0.246 0.000 u0|emif_0|emif_0_core_usr_clk
Info(332119): 0.539 0.000 u0|pcie_a10_hip_0|dut|tx_bonding_clocks[0]
Info(332119): 0.648 0.000 u0|emif_0|emif_0_phy_clk_l_0
Info(332119): 0.686 0.000 u0|emif_0|emif_0_phy_clk_l_2
Info(332119): 0.784 0.000 u0|emif_0|emif_0_phy_clk_l_1
Info(332119): 1.028 0.000 u0|pcie_a10_hip_0|dut|pld_clk
Info(332119): 2.197 0.000 u0|emif_0|emif_0_core_cal_master_clk
Info(332119): 3.658 0.000 u0|emif_0|emif_0_core_cal_slave_clk
Info(332119): 4.713 0.000 emif_0_pll_ref_clk
Info(332119): 11.949 0.000 altera_reserved_tck

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3 Replies
KennyT_Intel
Moderator
202 Views

Yes, it should not be allowed. This happened usually you use a different version of Quartus Prime.


This clock used for signal tap. What you can try is use different seeds to close the timing since the value is small.


KennyT_Intel
Moderator
192 Views

Any update?


KennyT_Intel
Moderator
177 Views

We do not receive any response from you to the previous question/reply/answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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