SoC system using Cyclone V development kit

[Mohammed_Lami]

Hello everyone, I am trying to create a SoC system using Cyclone V development kit to achieve a specific task. The following points illustrates what I have done so far before telling my question:

1) The design of SoC system including the "Cortex A9" HPS processor, on-chip mapped RAM, and an output device have been completed using "Qsys" system in "Quartus 14.1" software.
2) The "Pre-loader" and "U-boot" software have been completed using the "SoC EDS 14.1" command shell. Both files were stored in an SD-RAM to initiate the HPS.
3) The Quartus project has been compiled, the programming ".sof" file was created. The Cyclone V was programmed successfully by the Quartus programmer.
4) In the Quartus project, a ".hex" file was created in the project directory "...\synthesis\submodules". This file represents the program that will be stored in the RAM to be executed by the HPS in form of hexadecimal code "or intel hexadecimal format".

In my understanding, the code of the ".hex" file can be obtained as below:
A) Using one of ARM tools that match with the Cortex A9 HPS (inside the Cyclone V), the program can be written based on "C, C++, or Python" language.
B) After building the project using ARM tool, the compiler will interpret/convert the program to the ".hex" code.
C) The generated HEX code then can be copied to the "intel hexadecimal format" file of the RAM to be executed by the HPS.

Now my concerns are as below please:
I) Is what I think in points (A, B, and C) above is correct?
II) If it is correct, what kind of tool please that can be used to write the program and generate the ".hex" file?

Thank you for your support in advance

[aikeu]

Hi Mohammed_Lami,

I may not understanding what you are looking into.

There is a new boot flow that we use now which is found in this link:

https://rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Arria_10_SoC_45_Boot_from_QSPI

If you are checking on the older document I think this is the document that may help:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/an7091.pdf

Thanks.

Regards,

Aik Eu

[Mohammed_Lami]

Hi aikeu, thank you very much for your response

Actually, the boot flow is already done in my design. However, my concern in points (I and II), it is about how to generate the ".hex" file that contains the source code that should be executed by the A9 HPS processor.

As I explained, after the processor is booted successfully, I need to use it to execute a specific function. Previously, I used "ARM MDK Keil" software to write a "C" program, then the software generates the source code (inside the ".hex" file) after compiling the project; this code was copied to the directory of Quartus project and represented the contents of the on-chip RAM; after power on the FPGA board and booting the Cortex-M0 successfully, the processor accessed the RAM contents (source code of the ".hex" file) and ran it, this was done on Cyclone IV chip.

But now I am trying to execute another "C-code" on the Cyclone V dev. kit. My specific concern is generating of the source code that going to be stored at the on-chip RAM, the MDK tool can not work with A9 processor of Cyclone v. I also investigated ARM DS-5 tool, it is compatible with the A9 processor, but can't generate the source code seemingly.

Thank you

[aikeu]

Hi Mohammed_Lami,

I try to ask around and understand that we no longer support the Quartus 14 release as it is an older build flow which we no longer work with it. No relevant details that I can provide for your question.

The recommeded flow is to start with a GSRD https://rocketboards.org/foswiki/Documentation/CycloneVSoCGSRD

or with BuildingBootloader

https://rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Cyclone_V_SoC_45_Boot_from_SD_Card

I may not understand your question properly, If you are trying to boot from FPGA you can try with

https://rocketboards.org/foswiki/Documentation/BootFromFPGA140

Anyhow this is also a flow that we do not support anymore.

Thanks.

Regards,

Aik Eu

[Mohammed_Lami]

Hi aikeu, thank you very much for your response

Actually my question doesn't related to the version of Quartus software. In other words, the procedures that I had wondered about them are applicable even for the current versions of Quartus, like 20.1 and so on. When you mentioned "If you are trying to boot from FPGA you can try", the booting action is to initiate the on-chip A9 processor, but my enquiry is related to the program that will be executed by the processor after the successful initialization that is generated from the following process: "C-program" ==> compiling ==> then opcode generation.

[aikeu]

Hi Mohammed_Lami,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu