FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

SoCKit Hard DDR3 controller

Altera_Forum
Honored Contributor II
1,121 Views

Does anyone have a working example that uses the hard DDR3 controller to access memory from the FPGA? There are two examples (with and without qsys) of using DDR3 without the hard controller, but none that use it. Is there something wrong with the hard DDR3 controller? i'd think you would want to use it because it is faster and doesn't consume as many FPGA resources. 

Thanks.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
144 Views

Hi, I was hunting for a similar example some time back, and found an example for cyclone v gt here: 

https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html 

 

Download the kit installation, and after that search for "q_sys_hmc.qsys" in the examples folder
Altera_Forum
Honored Contributor II
144 Views

Thanks for the information. I ended up copying the terasic example that uses a soft memory controller for that project. I'll take a look at it and see if it's possible to port it to my sockit board.

Reply