FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5156 Discussions

Stacking two TeraASIC DE3 Boards

Altera_Forum
Honored Contributor II
738 Views

I am trying to run a design with 2 stacked Terasic DE3 boards. One of the designs works when they are not stacked but NIOS hangs with some memory verify errors when they are stacked together. Does anyone know if I have unused pins on both the top and bottom of the same corresponding connectors (HSTC-A), for signals that I am not using, may I just delete them from the assignment and top level files and only use those I am using on both boards or should I still keep the assignments?

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
73 Views

 

--- Quote Start ---  

I am trying to run a design with 2 stacked Terasic DE3 boards. One of the designs works when they are not stacked but NIOS hangs with some memory verify errors when they are stacked together. Does anyone know if I have unused pins on both the top and bottom of the same corresponding connectors (HSTC-A), for signals that I am not using, may I just delete them from the assignment and top level files and only use those I am using on both boards or should I still keep the assignments? 

--- Quote End ---  

 

 

You are the only one who knows if there's any unused pins or not :) 

 

If I were you, I'd still keep the same pin assignment generated by the DE3 System Builder because it shouldn't be the root cause of your problem, unless there's something wrong with it. Speak of which, if the pin assignment of your design is not generated by the DE3 System Builder, you might want to do so by following Chapter 4.6 of DE3 user manual when connecting multiple DE3 boards. 

 

Hope it helps, 

 

David from Terasic
Reply