Hi, I connected a 1-port ram to the ADC in my Stratix-III dsp kit. For some reason, every 150 clock cycles or so I drop some samples. I access the ram by using the "in system memory content editor" and plotting the result in matlab. I've attached a screenshot of my schematic and a picture of the resulting waveform.The clock is running at 125MHz, well below the M144K max speed. The ADC is running at 125MHz as well. Thanks for the help. Matt
where does your "clock" signal come from? If it isn't perfectly synchronized with the ADC clock you may loose some signals.If you are reading the memory contents while your design is still writing in memory then you'll get bad data, probably a mix of old and new samples, and this could explain what you see. You would need to stop writing to the memory once you've reached the last address, and only then read the memory contents.
Thanks, for the reply. Actually, I am reading and writing to the ram at the same time...reading via the in-system-memory editor. I'll see what I can do so that Im not doing that anymore.Thanks Matt