Statrix IV clock pins assigment (Terasic DE4 dev kit)

Altera_Forum · ‎01-26-2012

Dear community members,

We have a little doubt releated to DE4 dev kit by Terasic. We are developing a simple fan controller.

Initially, we have used DE4 System Builder projects as reference. As we could note, when we check CLOCK option there, the software assign about 12 pins releated to clock. But, as you can see on Altera's tutorial (How to Begin a Simple FPGA Design Tutorial) just one clock pin is assigned. Our little project use one clock input.

We are worried about clock pins not assigned. There are external PLLs connected to the FPGA through those not assigned pins. Can those pins be damaged by external PLLs outputs, if we don't assign clock pins to them?

Thanks in advance,

Ronaldo

Altera_Forum · ‎01-31-2012

Not assigned pins in altera devices will be in Z state.

so they will not damage anything.

more advanced engineers can correct me.

Altera_Forum · ‎01-31-2012

Thanks Bark for your answer! I couldn't find this info in Alteras Satatrix IV Handbook. :(

But I believe that you're right.

Altera_Forum · ‎01-31-2012

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But I believe that you're right.

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Don't just guess, use the tools to know!

The Quartus II tool generates a file;

Fitter->Pin Out

Look at that file. Also look at the setting for unused pins;

Assignments->Device, Device and Pin Options, Unused Pins.

The default for Stratix IV is "As input tri-stated with weak pull-up". However, for older devices this used to be "As output driving ground". So if you inherit an older project and blindly assume that unused pins are tri-stated by default, you could damage that board.

So, now you know :)

Cheers,

Dave