I am looking for a way to get data from the mSGDMA IP Core in FPGA portion and do some calculation with that data in HPS. The problem is that I have never worked with FPGA-to-HPS ( F2H ) bridge and I do not have any clue how to store those data to read in HPS portion. I am not planning to use external SDRAM.
In my mind, first I will connect the mSGDMA write master to HPS via F2H as below
As I know, the F2H is connected to L3 Interconnect and from that it can reach to peripherals. And I see the L3 interconnect also connects to On-Chip RAM.
So, my questions are ( or you guys can give me some hints 😁 ) :
My plan is pretty simple:
mSGDMA transfer data -> read those data -> do some calculation ( take 2 or more data and do adding, subtracting, ect. )
Any hint, comment or recommendation is appreciated . Thanks in advance!
There is an example design that demonstrate the data communication between FPGA and SDRAM controlled via the HPS:
>It is possible if your software code is smaller than the amount of memory available on the onchip RAM. It can increase access performance.
> Well, you cannot utilize the entire on-chip RAM blocks just for storing program code, thus needing additional RAM blocks depending on the complexity and functionality.
>The example design of the Datamover will help you a lot.