Storing bitstream in Startix V GS SI eval kit and transmitting through the transmitter.

[Sri_yerr]

Hi,

I am using Stratix V GS SI evaluation kit to load bitstreams in the memory and transmit them through the SMA transmitters. Could someone shed some light on how to do it or any design example?

Thanks

Srikanth

[CheePin_C_Intel]

Hi Srikanth,

As I understand it, you have some inquiries related to using the SV GS SI eval kit. It would be great if you could further elaborate on the specific application that you are targeting. For example, if you are trying to use transceiver or GPIO, what is the data rate that you are using, what is the protocol to be comply and etc.

Just to set a correct expectation. Generally we would address specific inquiry related to FPGA but not design implementation. However, I will try my best to assist to my best knowledge.

If you are using transceiver in your design, you can start with simple Native PHY design + TX PLL + reset controller and send fix data pattern through Native PHY TX. It is recommended for you to perform a Modelsim simulation prior to hardware testing to help isolating any functional related problem.

Please let me know if there is any concern. Thank you.

[Sri_yerr]

Hi,

I am using TXs . I have a pre processed bit streams of size 1 MB that I want to store in the memory and transmit them through the TXs at a rate of 8 to 10 GBPs. Could you please provide any base to start this thing or any examples or procedures would be help ful.

[Sri_yerr]

I want to transmit the bits in serial. Could you let me know if I need to follow a specific protocol for this. Thanks

[CheePin_C_Intel]

Hi Srikanth,

Thanks for your clarification that you will be using the transceiver TX to send serial data at 8G to 10G data rate. As I search through the web, there seems to be no specific simple example design on this. I have attached a Modelsim simulation example which was previously from wiki for your reference. To run the simulation, do the following:

1. Extract the ZIP

2. Change the working directory of Modelsim to the ZIP folder

3. Type "source simulation_setup.tcl"

4. Type "simulate" to start the compilation and simulation

Note that this example was targeted for Q15.0. You can try out to see if it still working on your side.

As I looked into the a.v file, it seems like it is connected to a constant pattern generator. You can replace this with your own pattern generator.

It is recommended for you to go through the following documentation for further details on the transceivers prior to performing testing:

1. Stratix V Device Handbook Volume 2: Transceivers - https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-v/stx5_xcvr.pdf

2. V-Series Transceiver PHY IP Core User Guide - https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/xcvr_user_guide.pdf

Please let me know if there is any concern. Thank you.

[CheePin_C_Intel]

Attaching the simulation example

[CheePin_C_Intel]

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[Sri_yerr]

Hi,

I am working on it. Could you please hold on for few more days on this before moving it it to community support.

Thank you