Stratix 10 1G/2.5G Ethernet reconfiguration not working in hardware

[AleCampla]

Hi,

i have ported the design of the 1G/2.5G Ethernet Design Example to the Stratix 10 MX.

I removed the loopback on the gmii side, the traffic controller and one of the two channels, as my design foresees only 1 channel.

After activating the "Enable Native PHY Debug Master Endpoint (NPDME)" option in the PHY (for some reasons this was not enable in the example design..), in simulation I manage to switch the configuration from 2.5G to 1G, as shown in the picture I am attaching to this post.

But when I try to do it on the Stratix10 dev kit, with the system console scripts coming with the example design, the configuration does not change.

TEST_ST_LB 0 1G -> is the command I use (where actually the channel number is not needed a used by the traffic controller that is anyway not instantiated).

What am I missing? 

Thanks a lot.

Alessandra

[Deshi_Intel]

Hi,

There are multiple example design in the design example link.

• May I know which example design that you used ?

For debug purpose,

• Can you use back example design without modifying too much in the design first ?
• Just to confirm you are connecting to S10 MX board H-tile transceiver, right ?
• Also, pls watch out to ensure you configure the correct clocking on S10 MX board and release the Ethernet IP reset properly
• Lastly, before you test out dynamic reconfig switching from 2.5G to 1G, have you try out fix 2.5G or 1G to see whether it works on S10 MX board ?

Thanks.

Regards,

dlim

[AleCampla]

Hi,

thanks for the fast reply!

Let me reply to your points.

There are multiple example design in the design example link.

• May I know which example design that you used ?

I am using the 1G/2.5G (as I am interested in establishing a 1G communication between the FPGA and my laptop).

For debug purpose,

• Can you use back example design without modifying too much in the design first ?

The example design can't be directly ported to S10 MX as some of the IPs are not available for the Stratix. In general I was able to run the original example simulation without problems.

And my simulation behaves well as the example simulation (picture from the previous post): via Avalon MM interface I can change the Multi Rate PHY speed, from the default (2.5, to the 1G).

To be more specific: what is in the design is a JTAG-to-Avalon MM bridge and a qsys project with address mapping (where I didn't change the address configuration, to avoid troubles with the scripts). And in my sim I was "injecting" the reconfiguration data just after the address mapping block. (I am planning to try now to do the data injection between the bridge and the mapping block, to see if there is some failure there).

• Just to confirm you are connecting to S10 MX board H-tile transceiver, right ?

This is correct.

• Also, pls watch out to ensure you configure the correct clocking on S10 MX board and release the Ethernet IP reset properly

For the clock, this is ok. Through the clock controller I am setting the rx_cdr_refclk to 125 MHz. And the PLLs to generare the remaining clocks are all properly locked.

For what concern the reset controller block, this is continuously sending a digitalreset to the Multi rate PHY, because the PHY rx_is_lockedtodata does not lock (when testing in hardware, while in simulation I am injecting some random data and the signal goes to 1, remaining stable). I imagine because no autonegotiation is happening (and no other data stream arrives). Here is also the origin of why I am trying to access the PHY registers during the hardware tests, and check/activate the autonegotiation settings.

• Lastly, before you test out dynamic reconfig switching from 2.5G to 1G, have you try out fix 2.5G or 1G to see whether it works on S10 MX board ?

So, as my main test concern the 1G configuration, while the default one is the 2.5G, I was able to set the 1G as default (just changing which .mif file should be picked up at the very beginning).

But due to rx_is_lockedtodata not locking in hardware I got a bit stuck.

Let me know if something is not clear and if you have any suggestion. Thanks for your help.

Alessandra

[AleCampla]

Hi,

I have been testing a bit more.

In simulation, injecting the avalon MM commands directly after the JTAG bridge to e.g. change the configuration of the PHY works well. So it's not a problem of the address mapping block.

To make sure that the read/write commands are actually propagated in hw, I added some counters on the read/write signal (simulation is ok).

BUT when I move to hardware and I launch the commands from the console, nothing is exiting the JTAG bridge. No counter is increasing, they all stay at zero.

It looks like, either the scripts or the Bridge is having an issue.

I am no sure on how to proceed with the debug. Let me know if you have suggestions.

Best regards,

Alessandra

Ps. more info on how I am using the console.

(i) Opening Quartus, (ii) uploading the firmware, (iii) opening the debug console.

I cd to the folder were the scripts are and after sourcing the main.tcl I am writing:

• reg_write 0x000000 0x0 0
• reg_write 0x000000 0x4 [expr ((1 << 16) | (0 << 0))]

that are the very same commands written in the rcfg/mge_rcfg_inc.tcl file (always from the example project) simply with the numbers explicitly written. (My MGE reconfig module has base address 0x00000000, like in the example project.)

And these correspond as well to the avalon mm commands that in simulation work.

[AleCampla]

Some more information:

Trought the get_service_paths master I discovered that the script was pointing to the wrong object on the jtag chain. It was set to 0, but now it's set to 1 (the stratix 10 MX on the devkit)

% get_service_paths master
{/devices/10M16S(A|C)@2#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/VTAP10@3#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master}

Still, I have no success as the requests timeout.

% set port_id [lindex [get_service_paths master] 1]
/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master
% open_service master $port_id

% master_read_32 $port_id 0x50000000 1
error: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.
while executing
"master_read_32 $port_id 0x50000000 1"

And no signals are propagated after the JTAG bridge.. could it be that the development kit of the S10 MX needs to be setup somehow?

[Deshi_Intel]

Hi,

Sorry for the late reply.

Look like you are still facing some issue in accessing the Ethernet design via system console.

My suggestion is maybe you can try with simpler design to ensure you can get system console working correctly with your S10 MX dev kit first.

For S10 MX dev kit board, you just need to ensure you have configure all the board jumper setting back to default position.

For debugging system console, the connection mainly is relying on JTAG connection.

• You can try reduce JTAG frequency lower from 24MHz to either 16MHz or even 6MHz
• Also make sure you have provided correct reset sequence and clock frequency to the reconfig clock of your Ethernet IP design.

Thanks.

Regards,

dlim

[AleCampla · Accepted solution]

Hi dlim,

I finally managed to communicate with the PHY.

One problem was that some of the switches were not in the right position, so the pointer in the scripts was not pointing to the S10 FPGA.

Also a reset_n on the fw side was not negated (and so it was always in resetting all the time).

This is then solved.

A part for one register (for auto negotiation enabling) that I can't write.

But I would open a new ticket for that.

Thanks for your support.

Alessandra

[Deshi_Intel]

HI,

Good. So you have found the issue to be the switch setting on board.

Alright, I am setting this case to closure.

Thanks.

Regards,

dlim