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Stratix 10 DX Development Kit Example Design Not Working

BigHandsomeBee
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I'm trying to compile the example design provided for Stratix 10 DX development kit, but the compilation failed.

However, the provided example sof file is working.

Below are the steps I have done:

 

1. Copy dx_golden_top (example design) folder to a custom destination.

2. Open dx_golden_top.qpf

3. Start compile

4. Two errors are reported: (1) Two ports are assigned to the same pins. After carefully comparing the provided qsf with the schematic, there is an error in qsf, and I fixed it. (2) Error "

Design requires 1076 user-specified I/O pins -- too many to fit in the 816 user I/O pin locations available in the selected device".

5. I did not find any information to fix the second error.

 

BigHandsomeBee_0-1624693579171.png

 

 

Urgently need some help. Thanks.

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JohnT_Intel
Employee
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Hi,


May I know if you have connected the XCVR IP to the Golden design? The reason is that the XCVR pin will not be assigned to pin connection if it is not connected to the XCVR IP. So I would recommend you to comment out the XVCR pin for PCIe or UPI interface if you are not using it.


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JohnT_Intel
Employee
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Hi,


May I know if you have connected the XCVR IP to the Golden design? The reason is that the XCVR pin will not be assigned to pin connection if it is not connected to the XCVR IP. So I would recommend you to comment out the XVCR pin for PCIe or UPI interface if you are not using it.


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JohnT_Intel
Employee
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Attach is the updated top level file which I commented out the XCVR ports.

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