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Stratix 10 JTAG to Avalon Master Bridge Exception

Altera_Forum
Honored Contributor II
1,002 Views

I am attempting to use the JTAG to Avalon Memory Map Master Bridge IP core with a Stratix 10 Signal Integrity Kit but when I program the board with the System Console I get an exception saying that no SLD nodes will be created for the device; I have also tried programming the board with the standalone programmer and communicate with the core through the system console but in that instance there is no exception but no reads or writes will finish. 

 

I first noticed this error with the 10G Ethernet MAC example design and have also created a project that only contains the JTAG core, a PIO, and clock and reset source that throws the same exception. When I remove the JTAG core from the example design it programs without issue but I am unable to test the rest of the functionality because the JTAG core is the only way I have to communicate with the chip.
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3 Replies
Altera_Forum
Honored Contributor II
179 Views

Can you show your Platform Designer System Contents? And what is the exact error message(s) you are getting?

Altera_Forum
Honored Contributor II
179 Views

Here's the simple Qsys system I'm trying to programming the board with and the system console after I've programmed the board. The error is shown in the messages window in the bottom left.

Altera_Forum
Honored Contributor II
179 Views

The pictures are too small to see. 

 

Is this system the entire design? Where is the clock coming from?
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