FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
4967 Discussions

Stratix 10- L tile SoC Dev kit: SignalTap hangs JTAG chain

HBhat2
New Contributor II
318 Views
Hi,
 
We are testing some DDR4 related logic on Stratix 10 Platform (Stratix 10 L tile SoC dev kit: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/strati...). We are seeing one issue wrt FPGA programming.
We kept MSEL to JTAG mode and programmed sof from Quartus programmer & FPGA gets programmed.
 
In the same sof, I enabled signalTAP. So, in order to test the design with the help of signalTAP, we open the signaltap file, the JTAG gets hanged. Once we scan chain in Signaltap windows, Quartus programmer is unable to program the FPGA once again. We need to power cycle the board to program the FPGA once again.
 
Also, we have changed the JTAG frequency to 6MHz and checked. It is same behaviour.
 
I have attached the Nios2command shell print wrt jtagconfig command prints.
 
Previously, we used signalTap for my design verification & it was working fine. If we use the previous working sof & .stp files, same behavior of JTAG hang is observed.  Is there any Quartus license required separately for SignalTap?
 
Can you guide us to locate the problem wrt SignalTap.
 
Note:  We tried with 2 SW positions as mentioned below & Same behavior is there wrt both the SW position 
 
SW1: OFF-OFF-ON-ON-ON-ON-ON-ON
SW2: All ON
SW3: All OFF
SW4: OFF-ON-OFF-ON
 
SW1: OFF-OFF-ON-ON-ON-ON-ON-ON
SW2: All ON
SW3: All OFF
SW4: ON-OFF-ON-OFF
 
With Regards,
HPB
0 Kudos
1 Solution
HBhat2
New Contributor II
281 Views

Hi,

I contacted local support team(Cytech) in Bangalore and got couple of suggestions.

As per the suggestions, I revisited the scenario & the problem was some java task related to JTAG is running in the background. I manually closed the task using Task Manager & relaunched Quartus & signaltap. Now everything looks fine.

With Regards,

HPB

View solution in original post

3 Replies
ShafiqY_Intel
Employee
303 Views

Hi HBhat2-GRL,

 

About your JTAG-hang sof file, do you able to program this sof successfully in your device?

 

Regards,

Matt

HBhat2
New Contributor II
297 Views

Hi,

Yes, I can program the sof (different sof files one after the other )to dev kit many times if I am not opening signaltap file & scan the chain.

However, If I open signatap & click scanchain, the JTAG chain gets hanged. After that I cant program any sof file.

If  I power cycle the board, then I can program the sof again.

 

With regards,

HPB

HBhat2
New Contributor II
282 Views

Hi,

I contacted local support team(Cytech) in Bangalore and got couple of suggestions.

As per the suggestions, I revisited the scenario & the problem was some java task related to JTAG is running in the background. I manually closed the task using Task Manager & relaunched Quartus & signaltap. Now everything looks fine.

With Regards,

HPB

View solution in original post

Reply