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Stratix 10 MX Development Kit - Low Latency 100G IP Core Design Example Problems

Larsgrantz
Novice
742 Views

Hi,

I am using the Stratix 10 MX (8 Gb) Development Board (Device: 1SM21BHU2F53E2VG) to test out the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example on Quartus v19.1.

I have reached step 1.8 in the design example user guide successfully, but I am getting a very weird results to no results. I have no idea why the IP core is not working as intended. I have attached the .qsf file, the System Console output, and the Ethernet link screenshots.

IP Core User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_ll_100gbe.pdf

Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-ll-100gbe.pdf

Thank you.

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1 Solution
SengKok_L_Intel
Moderator
732 Views

Hi,


By referring to the qsf file, it looks like you did not do the pin assignment correctly, you are testing the QSFP /100G ethernet, but you assign the clock and TX/RX Pin to PCIe. Please refer to the user guide or the schematic below for more detail:


https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/mx_fpga/s10mx_pcie_devkit.pdf


Regards -SK


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5 Replies
SengKok_L_Intel
Moderator
733 Views

Hi,


By referring to the qsf file, it looks like you did not do the pin assignment correctly, you are testing the QSFP /100G ethernet, but you assign the clock and TX/RX Pin to PCIe. Please refer to the user guide or the schematic below for more detail:


https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/mx_fpga/s10mx_pcie_devkit.pdf


Regards -SK


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Larsgrantz
Novice
707 Views

Hi Sengkok,

Thanks for pointing the incorrect pin assignment out!

Unfortunately, I am having the same poor results where nothing appears to be working. I have attached the updated qsf file.

Thanks,

Lars

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SengKok_L_Intel
Moderator
678 Views

Hi Lars,


You may check turn on the Internal serial loopback for this design example. If this is not working, then I suspect there might be something wrong with your clock source or pin assignment.


Regards -SK


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Larsgrantz
Novice
673 Views

Hi SengKok,

You were correct, it was a pin assignment problem. When I moved the clock pin from AG43 or CHT to AJ43 or CHB it started working.

Thanks for your help!

Lars

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SengKok_L_Intel
Moderator
656 Views

Hi Lars,


This is glad to see the problem resolved. If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


Regards -SK




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