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Stratix 10 SOC Development Kit example design qts_fmca_Q18.0.1_B261

MohanY
New Contributor I
348 Views

Hello,

 

I am trying to compile an example design for the Stratix 10 SOC Development Kit. 

Under Development Kit Documentation , I downloaded and installed
L-Tile Production (18.0.1 or higher)

Tried the following example from the examples folder with Quartus Prime Pro Version 18.0.1 Build 261 

example folder : qts_fmca_Q18.0.1_B261

Opened qts_fmca.qsf file

When compiled , it failed

Noticed the following entries under project -> add/remove file panel:
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_clk_50.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_user_tx_fifo_converter_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_freq_counter_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_tx_rx_clkout2_converter_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_user_rx_fifo_converter_0.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_rx_fifo.ip
../../../../../../../../../../p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_data_pattern_checker_0.ip
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/xcvr_test_system.qsys
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/cmos_test_system.qsys
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gx_2.qsys
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_cmos_system.qsys
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gx.qsys
../../../../../../../../../nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gxt.qsys

Removed , these entries and added them back , selecting them from  the qts_fmca folder. Now when I compile, I am getting the following errors:

Error (13225): Can't open VHDL or Verilog HDL file "ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_e7kc4bi.sv"
Error (13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_e7kc4bi.sv'
Error (13225): Can't open VHDL or Verilog HDL file "ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra.sv"
Error (13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra.sv'
Error (13225): Can't open VHDL or Verilog HDL file "ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra.sv"
Error (13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent/altera_xcvr_atx_pll_s10_htile_180/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra.sv'
Error (16045): Instance "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_gx2_1c|q_sys_xcvr_atx_pll_s10_htile_0" instantiates undefined entity "fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_e7kc4bi" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_gx2_1c|q_sys_xcvr_atx_pll_s10_htile_0" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1c_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_gx2_1c"
Error (16045): Instance "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent|q_sys_xcvr_atx_pll_s10_htile_0" instantiates undefined entity "fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent|q_sys_xcvr_atx_pll_s10_htile_0" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1d_above_adjacent" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/fmc_xcvr_system/synth/fmc_xcvr_system.v Line: 435
Error (16045): Instance "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent|q_sys_xcvr_atx_pll_s10_htile_0" instantiates undefined entity "fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent_altera_xcvr_atx_pll_s10_htile_180_44d53ra" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent|q_sys_xcvr_atx_pll_s10_htile_0" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/ip/fmc_xcvr_system/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent/synth/fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent.v Line: 229
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst|fmc_xcvr_system_xcvr_atx_pll_s10_htile_gxt_1f_above_adjacent" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/fmc_xcvr_system/synth/fmc_xcvr_system.v Line: 451
Error (16185): Can't elaborate user hierarchy "fmc_xcvr_system_inst" File: C:/Intel_designs/qts_fmca_Q18.0.1_B261/qts_fmca.v Line: 186
Error (16186): Can't elaborate top-level user hierarchy
Error: Flow failed:
Error: Quartus Prime Synthesis was unsuccessful. 18 errors, 51 warnings

I was hoping to be able to compile as downloaded without any edits. I am using th same Quartus edition, this example was supposedly built under. Appreciate any help.

0 Kudos
3 Replies
EBERLAZARE_I_Intel
317 Views

Hi,

 

Have you you tried opening the original and entire project file, ".qpf", then try recompiling it after opening the .qpf file.

MohanY
New Contributor I
310 Views

Yes. The following are the errors that I  get with Quartus Prime Pro 18.0.1 Build 261

 

Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_user_tx_fifo_converter_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_freq_counter_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_tx_rx_clkout2_converter_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_mm_bridge_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_data_pattern_generator_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_xcvr_user_rx_fifo_converter_0.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_rx_fifo.ip.
Error: Error opening C:/p/psg/board/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/ip/xcvr_test_system/xcvr_test_system_data_pattern_checker_0.ip.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/xcvr_test_system.qsys.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/cmos_test_system.qsys.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gx_2.qsys.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_cmos_system.qsys.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gx.qsys.
Error: Error opening C:/nfs/site/disks/psg_board_1/nwang/Stratix10_soc/reference_designs/RevA1_SX/Q18.0.1_B261_LTPRD/qts_fmca_Q18.0.1_B261/fmc_xcvr_test_gxt.qsys.
Error: Quartus Prime IP Generation Tool was unsuccessful. 15 errors, 0 warnings
Error: Peak virtual memory: 4717 megabytes
Error: Processing ended: Tue Jul 13 15:18:36 2021
Error: Elapsed time: 00:00:29
Error: Total CPU time (on all processors): 00:00:35
Error(293001): Quartus Prime Full Compilation was unsuccessful. 17 errors, 0 warnings

EBERLAZARE_I_Intel
248 Views

Hi,

 

Do you have a valid Quartus Pro license? Did you try to compile the GHRD instead if that would compiled succesfully.

Reply